Port Delay Register - Keysight VXI Bus 75000 C Series User And Programming Manual

Register Descriptions
EI (Enable Inhibit). This bit, if set to 1, enables the STS line to inhibit a transfer cycle
during a transfer. If bit 4 is set, the transfer is inhibited when the peripheral puts
STS in the BUSY state and resumes when STS returns to the READY state.
HT (5-7)(Handshake Type). These bits determine the type of handshake for port
input and output transfers as shown in Table B-4.

Port Delay Register

The Port Delay Register sets the delay time, Td. Delay time is the time between
data valid and setting the control (CTL) line TRUE. It is used with several
handshake modes. You can also read this register to find the current delay time.
The ports affected by this register are set by the BB1 and BB0 bits in the Card
Status/Control Register.
RM (0,1)(Range Multiplier). You can specify the range of delay time, Td, by selecting
the one of the range multipliers in Table B-5.
Keysight E1458A 96-Channel Digital I/O Module User Guide
Table B-4. Handshake Type
Output/Input Transfer
No Handshake
Leading Edge
Trailing Edge
Pulse
Partial
Strobe
base+3416, base+3516, base+3616, base +3716
7 6 5 4
DF7 DF6 DF5 DF4
Table B-5. Range Multipliers.
Range RM1 (Bit 1)
Multiplier
1 ms 0
µ
100 s 0
µ
10 s 1
µ
1 s 1
Keysight E1458A Register Information
Bit 7 Bit 6 Bit 5
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
3 2 1 0
— — RM1 RM0
RM0 (Bit 0)
0
1
0
1
133