HOLTEK BS82C16A-3 Manuals

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HOLTEK BS82C16A-3 Manual

HOLTEK BS82C16A-3 Manual (168 pages)

Touch Key 8-Bit Flash MCU with LED/LCD Driver

Brand: HOLTEK | Category: Microcontrollers | Size: 5 MB

Table of Contents

Cont�Ol Registe
1
Table of Contents
2
Ente�Ing the SLEEP Mode
4
Features

6
General Description

7
Selection Table

7
- Watchdog Time� Clock so
  7
- Watchdog Time� Cont�Ol Registe
  7
Block Diagram

8
Pin Assignment

8
Pin Descriptions

10
Absolute Maximum Ratings

17
D.C. Characteristics

18
Characteristics

20
Sensor Oscillator Electrical Characteristics

21
Power-On Reset Characteristics

24
System Architecture

25
- Clocking and Pipelining
  25
- P�Og�Am Co�Nte
  26
- Stack
  27
- A�Ithmetic and Logic Unit - ALU
  27
Flash Program Memory

28
- Special Vecto�S
  29
- Look-�P Table
  29
- On-Chip Deb�G S�Ppo�T - OCDS
  31
RAM Data Memory

32
Special Function Register Description

36
- Memo
  36
- Bank Pointe
  37
- Stat�S Registe� - STATUS
  39
EEPROM Data Memory

41
- EEPROM Data Memo
  41
- EEPROM Registe�S
  41
- W�Iting Data to the EEPROM
  43
- EEPROM Inte
  43
- P�Og�Amming Conside�Ations
  44
Oscillator

45
Operating Modes and System Clocks

48
- S�Stem Clocks
  48
- S�Stem Ope�Ation Modes
  50
- NORMAL Mode to SLOW Mode Switching
  53
- SLOW Mode to NORMAL Mode Switching
  54
- Ente�Ing the IDLE0 Mode
  55
- Wake
  56
Watchdog Timer

57
Reset and Initialisation

59
- Reset Initial Conditions
  61
Input/Output Ports

65
- I/O Registe� List
  65
- P�Ll-High Resisto�S
  66
- Po�T a Wake-�P
  66
- I/O Po�T Cont�Ol Registe�S
  66
- I/O Pin St
  66
- P�Og�Amming Conside�Ations
  68
Timer Modules - TM

69
- Int�Od�Ction
  69
- TM Ope�Ation
  69
- TM Clock so
  69
- TM Inte
  70
- TM Exte�Nal Pins
  70
- TM Inp�T/O�Tp�T Pin Cont�Ol Registe
  70
Compact Type TM - CTM0

74
Periodic Type TM - PTM0

85
- Pe�Iodic T�Pe TM Registe� Desc�Iption
  86
- Pe�Iodic T�Pe TM Ope�Ating Modes
  90
- Compa�E Match O�Tp�T Mode
  90
- PWM O�Tp�T Mode
  93
- Single P�Lse Mode
  95
- Capt
  97
Touch Key Function

99
- To�Ch Ke� St
  99
  - Touch Key Register Definition
    99
  - To�Ch Ke� Ope�Ation
    104
  - To�Ch Ke� Inte
    107
  - P�Og�Amming Conside�Ations
    107
I 2 C Interface

108
- I 2 C Inte�Face Ope�Ation
  108
- I 2 C Registe�S
  109
- I 2 C B�S Comm�Nication
  112
- I 2 C B�S Sta�T Signal
  113
- Slave Add�Ess
  113
- I 2 C B�S Read/W�Ite Signal
  114
- I 2 C B�S Slave Add�Ess Acknowledge Signal
  114
- I 2 C B�S Data and Acknowledge Signal
  114
- I 2 C Time-O�T Cont�Ol
  116
UART Interface

117
- UART Exte�Nal Pin Inte�Facing
  117
- UART Data T�Ansfe� Scheme
  118
- UART Stat�S and Cont�Ol Registe�S
  118
- Ba�D Rate Gene�Ato
  124
- UART T�Ansmitte
  127
- UART Receive
  128
- Managing Receive� E
  129
- UART Powe� down and Wake
  132
Interrupts

133
- Inte
  133
- Inte
  137
- Time Base Inte
  138
- TM Inte
  139
- EEPROM Inte
  139
- LVD Inte
  140
- To�Ch Ke� Inte
  140
- I 2 C Inte
  140
- UART Inte
  140
- Inte
  141
- P�Og�Amming Conside�Ations
  141
SCOM and SSEG Function for LCD

142
- LCD Ope�Ation
  142
- LCD Bias Cont�Ol
  144
Low Voltage Detector - LVD

146
- LVD Registe
  146
- LVD Ope�Ation
  147
Configuration Options

148
Application Circuit

149
Instruction Set

150
- Inst
  150
- Logical and Rotate Ope�Ation
  151
- Bit Ope�Ations
  151
Instruction Set Summary

152
Instruction Definition

154
Package Information

163

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