Dram Timing Settings - Intel 695AS User Manual

CMOS Setup Utility – Copyright(C) 1984-2000 Award Software
> DRAM Timing Settings
> AGP Function Settings
In-Order Queue
Concurrent PCI/Host
I/O Recovery Time
CPU to PCI Post Write
CPU to PCI Dynamic Burst
PCI Delay Transaction
Memory Parity/ECC Check
System BIOS Cacheable
Video RAM Cacheable
Memory Hole
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↑ ↓ → ← ↑ ↓ → ←
F5:Previous Values

DRAM Timing Settings

Please refer to section 3-6-1
AGP Function Settings
Please refer to section 3-6-2
Memory Hole
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved, it cannot be cached. The user information of peripherals that need to use this area of
system memory usually discusses their memory requirements. The settings are: Enabled and
Disabled.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at F0000h-FFFFFh, resulting in
better system performance. However, if any program writes to this memory area, a system
error may result. The settings are: Enabled and Disabled.
Video RAM Cacheable
Select Enabled allows caching of the video BIOS, resulting in better system performance.
However, if any program writes to this memory area, a system error may result. The settings
are: Enabled and Disabled.
Memory Parity/ECC Check
This function provides parity check of memory.
The choice is either Disabled or Enabled.
3-6-1 DRAM Timing Settings
CMOS Setup Utility – Copyright(C) 1984-2000 Award Software
Advanced Chipset Features
Press Enter
Press Enter
4-Level
Enabled
Disabled
Enabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
F6:Optimized Defaults
DRAM Timing Settings
29
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F7:Standard Defaults