Timing Requirements; Table 42. Ripple And Noise; Table 43. Output Voltage Timing - Intel S5000XVNSATA Specification

Intel® Workstation Board S5000XVN TPS
+3.3 V
50mVp-p
Note:
1.
2.
3.
4.
8.4.8

Timing Requirements

The following are the timing requirements for the power supply operation. The output voltages
must rise from 10% to within regulation limits (T
rise from 1.0 to 25 ms. All outputs must rise monotonically. Each output voltage shall reach
regulation within 50 ms (T
voltage shall fall out of regulation within 400 msec (T
The following tables and diagrams show the timing requirements for the power supply being
turned on and off via the AC input with PSON held low, and the PSON signal with the AC input
applied.
Item
T Output voltage rise time from each main output.
vout_rise
T All main outputs must be within regulation of each other within this
vout_on
time.
T All main outputs must leave regulation within this time.
vout_off
Note:
The 5VSB output voltage rise time is from 1.0 ms to 25 ms.
Revision 1.5

Table 42. Ripple and Noise

+5 V +12 V 1, 2, 3, 4
50mVp-p 120mVp-p
Maximum continuous total output power should not exceed 670 W.
Maximum continuous load on the combined 12 V output shall not exceed 48 A.
Peak load on the combined 12 V output shall not exceed 52 A.
Peak total DC output power should not exceed 730 W.
) of each other during turn on of the power supply. Each output
vout_on

Table 43. Output Voltage Timing

Description
Intel order number: D66403-006
Design and Environmental Specifications
-12 V +5 VSB
120mVp-p 50mVp-p
) within 5 to 70 ms. 5 VSB is allowed to
vout_rise
) of each other during turn off.
vout_off
Minimum
5.0
N/A
N/A
Maximum
1 1
70
50
400
Units
ms
ms
ms
63