Pin J-Link Connector - Segger J-Link User Manual

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16.1 20-pin J-Link connector

16.1.1 Pinout for JTAG
J-Link and J-Trace have a JTAG connector compati-
ble to ARM's Multi-ICE. The JTAG connector is a 20
way Insulation Displacement Connector (IDC) keyed
box header (2.54mm male) that mates with IDC
sockets mounted on a ribbon cable.
*On later J-Link products like the J-link ULTRA,
these pins are reserved for firmware extension pur-
poses. They can be left open or connected to GND in
normal debug environment. They are not essential
for JTAG/SWD in general.
The following table lists the J-Link / J-Trace JTAG pinout.
PIN SIGNAL
1 VTref
Not con-
2
nected
3 nTRST
5 TDI
7 TMS
9 TCK
11 RTCK
13 TDO
Table 16.1: J-Link / J-Trace pinout
J-Link / J-Trace (UM08001)
CHAPTER 16
TYPE
This is the target reference voltage. It is used to check if
the target has power, to create the logic-level reference for
Input the input comparators and to control the output logic levels
to the target. It is normally fed from Vdd of the target board
and must not have a series resistor.
NC This pin is not connected in J-Link.
JTAG Reset. Output from J-Link to the Reset signal of the
target JTAG port. Typically connected to nTRST of the target
Output
CPU. This pin is normally pulled HIGH on the target to avoid
unintentional resets when there is no connection.
JTAG data input of target CPU. It is recommended that this
Output pin is pulled to a defined state on the target board. Typically
connected to TDI of the target CPU.
JTAG mode set input of target CPU. This pin should be
Output pulled up on the target. Typically connected to TMS of the
target CPU.
JTAG clock signal to target CPU. It is recommended that this
Output pin is pulled to a defined state of the target board. Typically
connected to TCK of the target CPU.
Return test clock signal from the target. Some targets must
synchronize the JTAG inputs to internal clocks. To assist in
meeting this requirement, you can use a returned, and
Input retimed, TCK to dynamically control the TCK rate. J-Link
supports adaptive clocking, which waits for TCK changes to
be echoed correctly before making further changes. Con-
nect to RTCK if available, otherwise to GND.
JTAG data output from target CPU. Typically connected to
Input
TDO of the target CPU.
Target interfaces and adapters
V T r e f
n T R S T
T D I
T M S
T C K
R T C K
T D O
R E S E T
D B G R Q
5 V - S u p p ly
Description
© 2004-2017 SEGGER Microcontroller GmbH & Co. KG
1 2
N C
3 4 G N D
5 6 G N D
7 8 G N D
9 1 0 G N D
1 1 1 2 G N D
1 3 1 4 G N D *
1 5 1 6 G N D *
1 7 1 8 G N D *
1 9 2 0 G N D *