Segger J-Link User Manual page 202

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5.8.2.5 Type 4: Reset core & peripherals, halt after bootloader
Same as type 0, but bootloader is always executed. This reset strategy has been
designed for MCUs/CPUs which have a bootloader located in ROM which needs to run
at first, after reset (since it might initialize some target settings to their reset state).
When using this reset strategy, J-Link will let the bootloader run after reset and halts
the target immediately after the bootloader and before the target application is
started. This is the recommended reset strategy for LPC11xx and LPC13xx devices
where a bootloader should execute after reset to put the chip into the "real" reset
state.
5.8.2.6 Type 5: Reset core & peripherals, halt before bootloader
Basically the same as reset type 8. Performs a reset of core & peripherals and halts
the CPU immediately after reset. The ROM bootloader is NOT executed.
5.8.2.7 Type 6: Reset for Freescale Kinetis devices
Performs a via reset strategy 0 (normal) first in order to reset the core & peripherals
and halt the CPU immediately after reset. After the CPU is halted, the watchdog is
disabled, since the watchdog is running after reset by default. If the target applica-
tion does not feed the watchdog, J-Link loses connection to the device since it is
reset permanently.
5.8.2.8 Type 7: Reset for Analog Devices CPUs (ADI Halt after kernel)
Performs a reset of the core and peripherals by setting the SYSRESETREQ bit in the
AIRCR. The core is allowed to perform the ADI kernel (which enables the debug inter-
face) but the core is halted before the first instruction after the kernel is executed in
order to guarantee that no user application code is performed after reset.
5.8.2.9 Type 8: Reset core and peripherals
J-Link tries to reset both, core and peripherals by setting the SYSRESETREQ bit in the
AIRCR. VC_CORERESET in the DEMCR is also set to make sure that the CPU is halted
immediately after reset and before executing any instruction.
Reset procedure:
1. Make sure that the device halts immediately after reset (before it can execute any
instruction of the user application) by setting the VC_CORERESET in the DEMCR.
2. Reset the core and peripherals by setting the SYSRESETREQ bit in the AIRCR.
3. Wait for the S_RESET_ST bit in the DHCSR to first become high (reset active) and
then low (reset no longer active) afterwards.
4. Clear VC_CORERESET.
This type of reset may fail if:
• J-Link has no connection to the debug interface of the CPU because it is in a low
power mode.
• The debug interface is disabled after reset and needs to be enabled by a device
internal bootloader. This would cause J-Link to lose communication after reset
since the CPU is halted before it can execute the internal bootlader.
5.8.2.10 Type 9: Reset for LPC1200 devices
On the NXP LPC1200 devices the watchdog is enabled after reset and not disabled by
the bootloader, if a valid application is in the flash memory. Moreover, the watchdog
keeps counting if the CPU is in debug mode. When using this reset strategy, J-Link
performs a reset of the CPU and peripherals, using the SYSRESETREQ bit in the AIRCR
and halts the CPU after the bootloader has been performed and before the first
J-Link / J-Trace (UM08001)
CHAPTER 5
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Working with J-Link and J-Trace