Segger J-Link User Manual page 38

38
Target supply current
Reset Type
Reset low level output voltage (V
LOW level input voltage (V
HIGH level input voltage (V
LOW level output voltage (V
load of 10 kOhm
HIGH level output voltage (V
load of 10 kOhm
LOW level output voltage (V
load of 10 kOhm
HIGH level output voltage (V
load of 10 kOhm
SWO sampling frequency
Data input rise time (T
Data input fall time (T
Data output rise time (T
Data output fall time (T
Clock rise time (T
Clock fall time (T
Sampling frequency
Resolution
Table 1.3: J-link ULTRA specifications
1.3.4.3 Hardware versions
Version 1.1
Compatible to J-Link.
• Initial design based on ATMEL SAM3U without FPGA.
Version 4
• New design based on STM32F407 + FPGA (Cyclone IV)Version 4.3
Identical to version 4 with the following exception:
Pin 1 (VTref) is used for measuring target reference voltage only. Buffers on J-Link
side are no longer powered through this pin but via the J-Link internal voltage sup-
plied via USB.
1.3.4.4 Software and Hardware Features Overview
For detailed information about hardware and software features of your J-Link/J-Trace
model and version see:
https://wiki.segger.com/Software_and_Hardware_Features_Overview
J-Link / J-Trace (UM08001)
OL
For the whole target voltage range (1.8V <= V
)
IL
)
IH
For 1.8V <= V
) with a
OL
) with a
OH
For 3.6 <= V
) with a
OL
) with a
OH
JTAG/SWD Interface, Timing
)
rdi
)
fdi
)
rdo
)
fdo
)
rc
)
fc
Analog power measurement interface
CHAPTER 1
Max. 300mA
Open drain. Can be pulled low or
tristated.
) V <= 10% of V
OL
V <= 40% of V
IL
V >= 60% of V
IH
<= 3.6V
IF
V <= 10% of V
OL
V >= 90% of V
OH
<= 5V
IF
V <= 20% of V
OL
V >= 80% of V
OH
Max. 100 MHz
T <= 20ns
rdi
T <= 20ns
fdi
T <= 10ns
rdo
T <= 10ns
fdo
T <= 3ns
rc
T <= 3ns
fc
50 kHz
1 mA
© 2004-2017 SEGGER Microcontroller GmbH & Co. KG
Introduction
IF
<= 5V)
IF
IF
IF
IF
IF
IF
IF