Xilinx VC709 User Manual page 53

Table 1-20: VITA 57.1 FMC HPC J35 Connections to FPGA U1 (Cont'd)
J35 FMC
Schematic Net Name
HPC Pin
A35 FMC1_HPC_DP4_C2M_N
A38 FMC1_HPC_DP5_C2M_P
A39 FMC1_HPC_DP5_C2M_N
C2 FMC1_HPC_DP0_C2M_P
C3 FMC1_HPC_DP0_C2M_N
C6 FMC1_HPC_DP0_M2C_P
C7 FMC1_HPC_DP0_M2C_N
C10 FMC1_HPC_LA06_P
C11 FMC1_HPC_LA06_N
C14 FMC1_HPC_LA10_P
C15 FMC1_HPC_LA10_N
C18 FMC1_HPC_LA14_P
C19 FMC1_HPC_LA14_N
C22 FMC1_HPC_LA18_CC_P
C23 FMC1_HPC_LA18_CC_N
C26 FMC1_HPC_LA27_P
C27 FMC1_HPC_LA27_N
C30 FMC1_HPC_IIC_SCL
C31 FMC1_HPC_IIC_SDA
C34 GND
C35 VCC12_P
C37 VCC12_P
C39 VCC3V3
VC709 Evaluation Board
UG887 (v1.2.1) March 11, 2014
J64 FMC
U1 FPGA Pin
HPC Pin
J1 B36
H4 B37
H3 B40
E2 D1
E1 D4
D8 D5
D7 D8
K42 D9
J42 D11
N38 D12
M39 D14
N39 D15
N40 D17
M32 D18
L32 D20
J31 D21
H31 D23
U52.4 D24
U52.3 D26
NA D27
NA D29
NA D30
NA D31
D32
D33
D34
D35
D36
D38
D40
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Feature Descriptions
Schematic Net Name
FMC1_HPC_DP6_C2M_P
FMC1_HPC_DP6_C2M_N
NC
PWRCTL1_VCC4B_PG
FMC1_HPC_GBTCLK0_M2C_P
FMC1_HPC_GBTCLK0_M2C_N
FMC1_HPC_LA01_CC_P
FMC1_HPC_LA01_CC_N
FMC1_HPC_LA05_P
FMC1_HPC_LA05_N
FMC1_HPC_LA09_P
FMC1_HPC_LA09_N
FMC1_HPC_LA13_P
FMC1_HPC_LA13_N
FMC1_HPC_LA17_CC_P
FMC1_HPC_LA17_CC_N
FMC1_HPC_LA23_P
FMC1_HPC_LA23_N
FMC1_HPC_LA26_P
FMC1_HPC_LA26_N
FMC1_HPC_TCK_BUF
FMC1_TDI_BUF
FMC1_TDO_FPGA_TDI
VCC3V3
FMC1_HPC_TMS_BUF
NC
GND
VCC3V3
VCC3V3
VCC3V3
U1 FPGA
Pin
G2
G1
NA
AL32
G10
G9
J40
J41
M41
L41
R42
P42
H39
G39
L31
K32
P30
N31
J30
H30
U19.14
U19.18
T10
NA
U19.17
NA
NA
NA
NA
NA
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