Xilinx VC709 User Manual page 37

Table 1-10: PCIe Edge Connector Connections (Cont'd)
Net Name FPGA (U1) Pin
PCIE_TX6_P
PCIE_TX6_N
PCIE_TX7_P
PCIE_TX7_N
PCIE_CLK_Q0_P
PCIE_CLK_Q0_N
PCIE_PRSNT_B J49 2, 4, 6
PCIE_WAKE_B
PCIE_PERST_B
Table 1-11
Table 1-11: GTH Quad 115 PCIe Edge Connector Connections
Quad 115 Pin Name
MGTXTXP0_115_AE2
MGTXTXN0_115_AE1
MGTXRXP0_115_AC6
MGTXRXN0_115_AC5
MGTXTXP1_115_AC2
MGTXTXN1_115_AC1
MGTXRXP1_115_AB4
MGTXRXN1_115_AB3
MGTXTXP2_115_AA2
MGTXTXN2_115_AA1
VC709 Evaluation Board
UG887 (v1.2.1) March 11, 2014
PCIe Edge
Connector (P1)
Pin Name
AJ2 A43 PERp6
AJ1 A44 PERn6
AK4 A47 PERp7
AK3 A48 PERn7
AB8 A13 REFCLK+
AB7 A14 REFCLK-
A1 PRSNT#1
AV33 B11 WAKE#
AV35 A11 PERST
lists the PCIe edge connector connections for Quad 115.
FPGA
Net Name
(U1) Pin
AE2 PCIE_TX3_P
AE1 PCIE_TX3_N
AC6 PCIE_RX3_P
AC5 PCIE_RX3_N
AC2 PCIE_TX2_P
AC1 PCIE_TX2_N
AB4 PCIE_RX2_P
AB3 PCIE_RX2_N
AA2 PCIE_TX1_P
AA1 PCIE_TX1_N
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Function
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
differential clock pair
from PCIe
Integrated Endpoint block
differential clock pair
from PCIe
J49 Lane Size Select
jumper
Integrated Endpoint block
wake signal
Integrated Endpoint block
reset signal
PCIe Edge Connector
(P1)
Pin Pin Name
A29 PERp3
A30 PERn3
B27 PETp3
B28 PETn3
A25 PERp2
A26 PERn2
B23 PETp2
B24 PETn2
A21 PERp1
A22 PERn1
Feature Descriptions
FFG1761 Placement
GTHE2_CHANNEL_X1Y17
GTHE2_CHANNEL_X1Y17
GTHE2_CHANNEL_X1Y16
GTHE2_CHANNEL_X1Y16
MGT_BANK_115
MGT_BANK_115
NA
U1 FPGA Bank13 Pin AV33
U1 FPGA Bank13 Pin AV35
FFG1761 Placement
GTHE2_CHANNEL_X1Y20
GTHE2_CHANNEL_X1Y20
GTHE2_CHANNEL_X1Y20
GTHE2_CHANNEL_X1Y20
GTHE2_CHANNEL_X1Y21
GTHE2_CHANNEL_X1Y21
GTHE2_CHANNEL_X1Y21
GTHE2_CHANNEL_X1Y21
GTHE2_CHANNEL_X1Y22
GTHE2_CHANNEL_X1Y22
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