Xilinx VC709 User Manual page 78

For the virtex-7 fpga
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Appendix C: Master XDC Listing
78
set_property PACKAGE_PIN AR12 [get_ports DDR3_B_DQS5_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_B_DQS5_N]
set_property PACKAGE_PIN AR15 [get_ports DDR3_B_D47]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D47]
set_property PACKAGE_PIN AT15 [get_ports DDR3_B_D46]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D46]
set_property PACKAGE_PIN AT12 [get_ports DDR3_B_D42]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D42]
set_property PACKAGE_PIN AU12 [get_ports DDR3_B_D40]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D40]
set_property PACKAGE_PIN AV15 [get_ports DDR3_B_DM5]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_DM5]
set_property PACKAGE_PIN AW15 [get_ports DDR3_B_D33]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D33]
set_property PACKAGE_PIN AW12 [get_ports DDR3_B_D36]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D36]
set_property PACKAGE_PIN AY12 [get_ports DDR3_B_D38]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D38]
set_property PACKAGE_PIN BA15 [get_ports DDR3_B_DQS4_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_B_DQS4_P]
set_property PACKAGE_PIN BA14 [get_ports DDR3_B_DQS4_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_B_DQS4_N]
set_property PACKAGE_PIN AY14 [get_ports DDR3_B_D32]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D32]
set_property PACKAGE_PIN AY13 [get_ports DDR3_B_D37]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D37]
set_property PACKAGE_PIN BB14 [get_ports DDR3_B_D34]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D34]
set_property PACKAGE_PIN BB13 [get_ports DDR3_B_D35]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D35]
set_property PACKAGE_PIN BA12 [get_ports DDR3_B_D39]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D39]
set_property PACKAGE_PIN BB12 [get_ports DDR3_B_DM4]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_DM4]
set_property PACKAGE_PIN AL19 [get_ports DDR3_B_A15]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A15]
set_property PACKAGE_PIN AM19 [get_ports DDR3_B_A14]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A14]
set_property PACKAGE_PIN AK17 [get_ports DDR3_B_A13]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A13]
set_property PACKAGE_PIN AL17 [get_ports DDR3_B_A12]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A12]
set_property PACKAGE_PIN AM18 [get_ports DDR3_B_A11]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A11]
set_property PACKAGE_PIN AM17 [get_ports DDR3_B_A10]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A10]
set_property PACKAGE_PIN AK19 [get_ports DDR3_B_A9]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A9]
set_property PACKAGE_PIN AK18 [get_ports DDR3_B_A8]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A8]
set_property PACKAGE_PIN AM16 [get_ports DDR3_B_A7]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A7]
set_property PACKAGE_PIN AN16 [get_ports DDR3_B_A6]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A6]
set_property PACKAGE_PIN AJ18 [get_ports DDR3_B_A5]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A5]
set_property PACKAGE_PIN AP18 [get_ports DDR3_B_A4]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_A4]
set_property PACKAGE_PIN AP17 [get_ports DDR3_B_A3]
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VC709 Evaluation Board
UG887 (v1.2.1) March 11, 2014

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