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Chapter 1: VC709 Evaluation Board Features
Table 1-8: Clock Connections, Source to FPGA
System Clock (SYSCLK_P and SYSCLK_N)
[Figure
The VC709 board has an LVDS 200 MHz oscillator (U51) soldered onto the back side of the
board and wired to an FPGA MRCC clock input on bank 38. This 200 MHz signal pair is
named SYSCLK_P and SYSCLK_N, which are connected to FPGA U1 pins H19 and G18
respectively.
•
•
•
The LVDS termination resistor R2, located within the FPGA via matrix on the bottom of the
board, is not populated. One possible I/O standard for the FPGA design clock input is:
For more details, see the
Figure
26
Clock Source Pin
J31.1
U24.29
U24.28
U13.5
U13.4
U40.3
1-2, callout 5]
Oscillator: Si Time SiT9102AI-243N25E200.00000 (200 MHz)
PPM frequency jitter: 50 ppm
Differential output
NET "sysclk_p"
LOC = "H19" | IOSTANDARD = DIFF_SSTL15_DCI | #Bank 38
MRCC input
NET "sysclk_n"
LOC = "G18" | IOSTANDARD = DIFF_SSTL15_DCI | #Diff.
Rterm R2 DNP
Si Time
1-7.
www.xilinx.com
Net Name
USER_SMA_CLOCK_P
Si5324_OUT_N
Si5324_OUT_P
SYSCLK_233_N
SYSCLK_233_P
FPGA_EMCCLK
SiT9102 data sheet. The system clock circuit is shown in
FPGA (U1) Pin
AJ32
AD7
AD8
AY17
AY18
AP37
VC709 Evaluation Board
UG887 (v1.2.1) March 11, 2014
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