Xilinx VC709 User Manual page 86

For the virtex-7 fpga
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Appendix C: Master XDC Listing
86
set_property PACKAGE_PIN E23 [get_ports DDR3_A_D44]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D44]
set_property PACKAGE_PIN E24 [get_ports DDR3_A_D40]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D40]
set_property PACKAGE_PIN F22 [get_ports DDR3_A_D46]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D46]
set_property PACKAGE_PIN E22 [get_ports DDR3_A_D47]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D47]
set_property PACKAGE_PIN F25 [get_ports DDR3_A_DQS5_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_A_DQS5_P]
set_property PACKAGE_PIN E25 [get_ports DDR3_A_DQS5_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_A_DQS5_N]
set_property PACKAGE_PIN D22 [get_ports DDR3_A_D45]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D45]
set_property PACKAGE_PIN D23 [get_ports DDR3_A_D41]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D41]
set_property PACKAGE_PIN D25 [get_ports DDR3_A_DM5]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_DM5]
set_property PACKAGE_PIN D26 [get_ports DDR3_A_D42]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D42]
set_property PACKAGE_PIN C25 [get_ports DDR3_A_D43]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D43]
set_property PACKAGE_PIN D27 [get_ports DDR3_A_D49]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D49]
set_property PACKAGE_PIN D28 [get_ports DDR3_A_D52]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D52]
set_property PACKAGE_PIN C28 [get_ports DDR3_A_D51]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D51]
set_property PACKAGE_PIN B28 [get_ports DDR3_A_DQS6_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_A_DQS6_P]
set_property PACKAGE_PIN B29 [get_ports DDR3_A_DQS6_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_A_DQS6_N]
set_property PACKAGE_PIN A31 [get_ports DDR3_A_D54]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D54]
set_property PACKAGE_PIN A32 [get_ports DDR3_A_D55]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D55]
set_property PACKAGE_PIN A29 [get_ports DDR3_A_D50]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D50]
set_property PACKAGE_PIN A30 [get_ports DDR3_A_D48]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D48]
set_property PACKAGE_PIN C31 [get_ports DDR3_A_DM6]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_DM6]
set_property PACKAGE_PIN B31 [get_ports DDR3_A_D53]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D53]
set_property PACKAGE_PIN E30 [get_ports DDR3_A_D56]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D56]
set_property PACKAGE_PIN D30 [get_ports DDR3_A_D63]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D63]
set_property PACKAGE_PIN C30 [get_ports DDR3_A_D60]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D60]
set_property PACKAGE_PIN E27 [get_ports DDR3_A_DQS7_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_A_DQS7_P]
set_property PACKAGE_PIN E28 [get_ports DDR3_A_DQS7_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_A_DQS7_N]
set_property PACKAGE_PIN F29 [get_ports DDR3_A_D57]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D57]
set_property PACKAGE_PIN E29 [get_ports DDR3_A_D61]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D61]
set_property PACKAGE_PIN F26 [get_ports DDR3_A_D62]
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VC709 Evaluation Board
UG887 (v1.2.1) March 11, 2014

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