Xilinx VC709 User Manual page 88

Appendix C: Master XDC Listing
88
set_property PACKAGE_PIN J18 [get_ports DDR3_A_CKE1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_CKE1]
set_property PACKAGE_PIN F20 [get_ports DDR3_A_WE_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_WE_B]
set_property PACKAGE_PIN E20 [get_ports DDR3_A_RAS_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_RAS_B]
set_property PACKAGE_PIN K17 [get_ports DDR3_A_CAS_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_CAS_B]
set_property PACKAGE_PIN J17 [get_ports DDR3_A_S0_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_S0_B]
set_property PACKAGE_PIN J20 [get_ports DDR3_A_S1_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_S1_B]
set_property PACKAGE_PIN H20 [get_ports DDR3_A_ODT0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_ODT0]
set_property PACKAGE_PIN H18 [get_ports DDR3_A_ODT1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_ODT1]
set_property PACKAGE_PIN G17 [get_ports DDR3_A_TEMP_EVENT_B]
set_property IOSTANDARD LVCMOS15 [get_ports DDR3_A_TEMP_EVENT_B]
set_property PACKAGE_PIN P18 [get_ports DDR3_A_RESET_B]
set_property IOSTANDARD LVCMOS15 [get_ports DDR3_A_RESET_B]
set_property PACKAGE_PIN C16 [get_ports DDR3_A_D30]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D30]
set_property PACKAGE_PIN B16 [get_ports DDR3_A_D26]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D26]
set_property PACKAGE_PIN B14 [get_ports DDR3_A_D24]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D24]
set_property PACKAGE_PIN A14 [get_ports DDR3_A_DM3]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_DM3]
set_property PACKAGE_PIN C15 [get_ports DDR3_A_DQS3_P]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_DQS3_P]
set_property PACKAGE_PIN C14 [get_ports DDR3_A_DQS3_N]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_DQS3_N]
set_property PACKAGE_PIN D13 [get_ports DDR3_A_D28]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D28]
set_property PACKAGE_PIN C13 [get_ports DDR3_A_D25]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D25]
set_property PACKAGE_PIN D16 [get_ports DDR3_A_D31]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D31]
set_property PACKAGE_PIN D15 [get_ports DDR3_A_D27]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D27]
set_property PACKAGE_PIN E12 [get_ports DDR3_A_D29]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D29]
set_property PACKAGE_PIN E15 [get_ports DDR3_A_D16]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D16]
set_property PACKAGE_PIN E14 [get_ports DDR3_A_D19]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D19]
set_property PACKAGE_PIN E13 [get_ports DDR3_A_D17]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D17]
set_property PACKAGE_PIN H16 [get_ports DDR3_A_DQS2_P]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_DQS2_P]
set_property PACKAGE_PIN G16 [get_ports DDR3_A_DQS2_N]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_DQS2_N]
set_property PACKAGE_PIN G12 [get_ports DDR3_A_D21]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D21]
set_property PACKAGE_PIN F12 [get_ports DDR3_A_DM2]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_DM2]
set_property PACKAGE_PIN F15 [get_ports DDR3_A_D18]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D18]
set_property PACKAGE_PIN F14 [get_ports DDR3_A_D22]
www.xilinx.com VC709 Evaluation Board
UG887 (v1.2.1) March 11, 2014