Xilinx VC709 User Manual page 80

Appendix C: Master XDC Listing
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set_property PACKAGE_PIN AL21 [get_ports DDR3_B_D10]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D10]
set_property PACKAGE_PIN AM21 [get_ports DDR3_B_D11]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D11]
set_property PACKAGE_PIN AJ21 [get_ports DDR3_B_D12]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D12]
set_property PACKAGE_PIN AJ20 [get_ports DDR3_B_D13]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D13]
set_property PACKAGE_PIN AL22 [get_ports DDR3_B_DM1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_DM1]
set_property PACKAGE_PIN AM24 [get_ports DDR3_B_D1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D1]
set_property PACKAGE_PIN AN24 [get_ports DDR3_B_D0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D0]
set_property PACKAGE_PIN AM23 [get_ports DDR3_B_D5]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D5]
set_property PACKAGE_PIN AN23 [get_ports DDR3_B_D4]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D4]
set_property PACKAGE_PIN AP23 [get_ports DDR3_B_DQS0_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_B_DQS0_P]
set_property PACKAGE_PIN AP22 [get_ports DDR3_B_DQS0_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_B_DQS0_N]
set_property PACKAGE_PIN AN21 [get_ports DDR3_B_D6]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D6]
set_property PACKAGE_PIN AP21 [get_ports DDR3_B_D7]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D7]
set_property PACKAGE_PIN AR23 [get_ports DDR3_B_D3]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D3]
set_property PACKAGE_PIN AR22 [get_ports DDR3_B_D2]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D2]
set_property PACKAGE_PIN AT22 [get_ports DDR3_B_DM0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_DM0]
set_property PACKAGE_PIN AU23 [get_ports DDR3_B_D20]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D20]
set_property PACKAGE_PIN AV23 [get_ports DDR3_B_D21]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D21]
set_property PACKAGE_PIN AW23 [get_ports DDR3_B_D17]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D17]
set_property PACKAGE_PIN AW22 [get_ports DDR3_B_D16]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D16]
set_property PACKAGE_PIN AT21 [get_ports DDR3_B_DQS2_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_B_DQS2_P]
set_property PACKAGE_PIN AU21 [get_ports DDR3_B_DQS2_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_B_DQS2_N]
set_property PACKAGE_PIN AR24 [get_ports DDR3_B_D22]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D22]
set_property PACKAGE_PIN AT24 [get_ports DDR3_B_D23]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D23]
set_property PACKAGE_PIN AV21 [get_ports DDR3_B_D19]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D19]
set_property PACKAGE_PIN AW21 [get_ports DDR3_B_D18]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D18]
set_property PACKAGE_PIN AU24 [get_ports DDR3_B_DM2]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_DM2]
set_property PACKAGE_PIN AY23 [get_ports DDR3_B_D26]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D26]
set_property PACKAGE_PIN AY25 [get_ports DDR3_B_D28]
set_property IOSTANDARD SSTL15 [get_ports DDR3_B_D28]
set_property PACKAGE_PIN BA25 [get_ports DDR3_B_D29]
www.xilinx.com VC709 Evaluation Board
UG887 (v1.2.1) March 11, 2014