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Chapter 1: VC709 Evaluation Board Features
X-Ref Target - Figure 1-8
User SMA Clock (USER_SMA_CLOCK_P and USER_SMA_CLOCK_N)
[Figure
An external high-precision clock signal can be provided to the FPGA bank 14 by
connecting differential clock signals through the onboard 50Ω SMA connectors J31 (P) and
J32 (N). The differential clock signal names are USER_SMA_CLOCK_P and
USER_SMA_CLOCK_N, which are connected to FPGA U1 pins AJ32 and AK32
respectively. The user-provided 1.8V differential clock circuit is shown in
X-Ref Target - Figure 1-9
GTH SMA Clock (SMA_MGT_REFCLK_P and SMA_MGT_REFCLK_N)
[Figure
The VC709 board includes a pair of SMA connectors for a GTH clock wired to GTH Quad
bank 113. This differential clock has signal names SMA_MGT_REFCLK_P and
SMA_REFCLK_N, which are connected to FPGA U1 pins AK8 and AK7 respectively.
28
VCC3V3
R15
4.7KΩ 5%
USER CLOCK SDA
To I 2 C
Bus Switch
USER CLOCK SCL
(U52)
GND
1-2, callout 7]
SMA
Connector
SMA
Connector
Figure 1-9: User SMA Clock Source
1-2, callout 8]
www.xilinx.com
U34
Si570
Programmable
Oscillator
1
6
NC
VDD
2
OE
7
5
USER CLOCK N
SDA
CLK-
8
USER CLOCK P
4
SCL
CLK+
3
GND
Figure 1-8: User Clock Source
J31
USER_SMA_CLOCK_P
J32
GND
USER_SMA_CLOCK_N
GND
VCC3V3
C192
0.01 μF 25V
X7R
GND
10 MHz – 810 MHz
50 PPM
UG887_c1_08_090612
Figure
UG887_c1_09_090612
VC709 Evaluation Board
UG887 (v1.2.1) March 11, 2014
1-9.
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