I 2 C Bus - Xilinx VC709 User Manual

Table 1-15: USB Connector J17 Pin Assignments and Signal Definitions
USB Connector (J17)
Pin Name
1 VBUS USB_UART_VBUS
2 D_N USB_D_N
3 D_P USB_D_P
4 GND USB_UART_GND
Table 1-16
Table 1-16: FPGA to UART Connections
FPGA
(U1)
Pin Function
AR34 RTS
AT32 CTS
AU36 TX
AU33 RX
Refer to the
drivers.
2
I C Bus
[Figure
The VC709 board implements a single I
IIC_SDA_SCL, pin AT35), which is routed through a TI Semiconductor PCA9548A 1-to-8
channel I
The bus switch I
to select the desired downstream device.
The four SFP+ connectors SFP1 (P3), SFP2 (P2), SFP3 (P4), and SFP4 (P5) are addressed
through a secondary PCA9546A 1-to-4 channel I
bus topology is shown in
VC709 Evaluation Board
UG887 (v1.2.1) March 11, 2014
Net Name
+5V VBUS powered
Bidirectional differential serial data (N-side)
Bidirectional differential serial data (P-side)
Signal ground
shows the USB connections between the FPGA and the UART.
Direction IO Standard
Output LVCMOS18
Input LVCMOS18
Output LVCMOS18
Input LVCMOS18
Silicon Labs website for technical information on the CP2103GM and the VCP
1-2, callout 14, 15]
2
C bus switch (U52). The bus switch can operate at speeds up to 400 kHz.
2
C address is 0x74 (0b01110100) and must be addressed and configured
Figure
www.xilinx.com
Description
Schematic CP2103GM
Net Name UART (U44)
Pin
USB_UART_CTS 22
USB_UART_RTS 23
USB_UART_RX 24
USB_UART_TX 25
2
C port on the FPGA (IIC_SDA_MAIN, pin AU32;
2
C bus switch (U14). The VC709 board I
1-17.
Feature Descriptions
CP2103GM (U44)
Pin Name
7 REGIN
8 VBUS
4 D –
3 D +
2 GND1
29 CNR_GND
Function Direction
CTS Input
RTS Output
RXD Input
TXD Output
2
C
43