Xilinx VC709 User Manual page 35

X-Ref Target - Figure 1-14
PCIe lane width/size is selected through jumper J49
selection is 1-lane (J49 pins 1 and 2 jumpered).
X-Ref Target - Figure 1-15
Table 1-10
Table 1-10: PCIe Edge Connector Connections
Net Name FPGA (U1) Pin
PCIE_RX0_P
PCIE_RX0_N
PCIE_RX1_P
PCIE_RX1_N
PCIE_RX2_P
PCIE_RX2_N
PCIE_RX3_P
PCIE_RX3_N
PCIE_RX4_P
VC709 Evaluation Board
UG887 (v1.2.1) March 11, 2014
P1
PCI Express
Eight-Lane
Edge Connector
GND
REFCLK+
REFCLK-
GND
Figure 1-15: PCI Express Lane Size Select Jumper J49
lists the PCIe edge connector connections at P1.
PCIe Edge
Connector (P1)
Pin Name
Y4 B14 PETp0
Y3 B15 PETn0
AA6 B19 PETp1
AA5 B20 PETn1
AB4 B23 PETp2
AB3 B24 PETn2
AC6 B27 PETp3
AC5 B28 PETn3
AD4 B33 PETp4
www.xilinx.com
OE
A12
A13
PCIE_CLK_Q0_C_P
A14 PCIE_CLK_Q0_C_N
A15
GND
Figure 1-14: PCI Express Clock
J49
PCIE_PRSNT_X1
1 2
PCIE_PRSNT_X4
3 4
PCIE_PRSNT_X8
5 6
Function
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Feature Descriptions
C544
0.01μF 25V
X7R
PCIE_CLK_Q0_P
PCIE_CLK_Q0_N
C545
0.01μF 25V
X7R
UG887_c1_13_090612
(Figure 1-15). The default lane size
PCIE_PRSNT_B
UG887_c1_14_083112
FFG1761 Placement
GTHE2_CHANNEL_X1Y23
GTHE2_CHANNEL_X1Y23
GTHE2_CHANNEL_X1Y22
GTHE2_CHANNEL_X1Y22
GTHE2_CHANNEL_X1Y21
GTHE2_CHANNEL_X1Y21
GTHE2_CHANNEL_X1Y20
GTHE2_CHANNEL_X1Y20
GTHE2_CHANNEL_X1Y19
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