Memory Clock (Sysclk_233_P And Sysclk_233_N) - Xilinx VC709 User Manual

Chapter 1: VC709 Evaluation Board Features
X-Ref Target - Figure 1-11
X6
114.285 MHz
20 ppm
2 XA
GND1
GND2 XB
4
GND
REC_CLOCK_C_P
R167
100Ω
REC_CLOCK_C_N
SI5326_INT_ALM
SI5326_RST
2.

Memory Clock (SYSCLK_233_P and SYSCLK_233_N)

[Figure
The VC709 board has a LVDS 233.3333 MHz oscillator (U13) soldered onto the back side of
the board and wired to an FPGA MRCC clock input on bank 32. This 233.3333 MHz signal
pair is named SYSCLK_233_P and SYSCLK_233_N. The P and N signals are connected to
FPGA U1 pins AY18 and AY17 respectively.
•
•
•
The LVDS termination resistor R43 is located within the FPGA via matrix on the bottom of
the board, and is not populated.
30
SI5324_VCC
5
10
32
1
SI5326_XTAL_XA 6
3 SI5326_XTAL_XB
7
C33
0.1μF 25V
X5R
REC_CLOCK_P 16
REC_CLOCK_N 17
NC 12
C34
0.1μF 25V
NC 13
X5R
3
NC 4
NC 11
NC 15
NC 18
19
20
1
21
R16
4.7KΩ 5%
GND
Figure 1-11: Jitter-Attenuated Clock
See the
Silicon Labs Si5324 data sheet for more information on this device.
1-2, callout 27]
Oscillator: Si Time SIT9122AC-2D3-25E233.333333 (233.3333 MHz)
PPM frequency jitter: 50 ppm
Differential output
www.xilinx.com
U24
Si5324C-C-GM
Clock Multiplier/
Jitter Attenuator
2
NC
VDD1 NC1
9
NC
VDD2 NC2
14
NC
VDD3 NC3
30
NC
XA NC4
33
NC
NC5
29
SI5326_OUT_N
XB CKOUT1_N
28
SI5326_OUT_P
CKOUT1_P
35
NC
CKIN1_P
CKOUT2_P
34
NC
CKOUT2_N
CKIN1_N
CKIN2_P
CKIN2_N
37
GNDPAD
36
INT_C1B CMODE
27
C2B SDI
23
RATE0 SDA_SDO
22
RATE1 SCL
24
LOL A0
31
GND3 A1
31
GND4 A2_SS
9
RST_B
GND1
31
CS_CA GND2
GND
C31
0.1μF 25V
X5R
SI5326_OUT_C_N
SI5326_OUT_C_P
C32
0.1μF 25V
X5R
NC
SI5326_SDA
SI5326_SCL
UG887_c1_11_090612
VC709 Evaluation Board
UG887 (v1.2.1) March 11, 2014