Xilinx VC709 User Manual page 87

VC709 Evaluation Board
UG887 (v1.2.1) March 11, 2014
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D62]
set_property PACKAGE_PIN F27 [get_ports DDR3_A_D59]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D59]
set_property PACKAGE_PIN F30 [get_ports DDR3_A_D58]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_D58]
set_property PACKAGE_PIN F31 [get_ports DDR3_A_DM7]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_DM7]
set_property PACKAGE_PIN C19 [get_ports DDR3_A_A9]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A9]
set_property PACKAGE_PIN B19 [get_ports DDR3_A_A1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A1]
set_property PACKAGE_PIN A16 [get_ports DDR3_A_A5]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A5]
set_property PACKAGE_PIN A15 [get_ports DDR3_A_A12]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A12]
set_property PACKAGE_PIN A20 [get_ports DDR3_A_A0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A0]
set_property PACKAGE_PIN A19 [get_ports DDR3_A_A3]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A3]
set_property PACKAGE_PIN B17 [get_ports DDR3_A_A11]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A11]
set_property PACKAGE_PIN A17 [get_ports DDR3_A_A4]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A4]
set_property PACKAGE_PIN B21 [get_ports DDR3_A_A10]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A10]
set_property PACKAGE_PIN A21 [get_ports DDR3_A_A13]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A13]
set_property PACKAGE_PIN C18 [get_ports DDR3_A_A7]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A7]
set_property PACKAGE_PIN D20 [get_ports DDR3_A_A6]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A6]
set_property PACKAGE_PIN C20 [get_ports DDR3_A_A2]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A2]
set_property PACKAGE_PIN F17 [get_ports DDR3_A_A14]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A14]
set_property PACKAGE_PIN E17 [get_ports DDR3_A_A15]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A15]
set_property PACKAGE_PIN D21 [get_ports DDR3_A_BA0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_BA0]
set_property PACKAGE_PIN C21 [get_ports DDR3_A_BA1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_BA1]
set_property PACKAGE_PIN D18 [get_ports DDR3_A_BA2]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_BA2]
set_property PACKAGE_PIN D17 [get_ports DDR3_A_A8]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_A8]
set_property PACKAGE_PIN G19 [get_ports DDR3_A_CLK1_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_A_CLK1_P]
set_property PACKAGE_PIN F19 [get_ports DDR3_A_CLK1_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_A_CLK1_N]
set_property PACKAGE_PIN E19 [get_ports DDR3_A_CLK0_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_A_CLK0_P]
set_property PACKAGE_PIN E18 [get_ports DDR3_A_CLK0_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_A_CLK0_N]
set_property PACKAGE_PIN H19 [get_ports SYSCLK_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports SYSCLK_P]
set_property PACKAGE_PIN G18 [get_ports SYSCLK_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports SYSCLK_N]
set_property PACKAGE_PIN K19 [get_ports DDR3_A_CKE0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_A_CKE0]
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VC709 Board XDC Listing
87