Xilinx VC709 User Manual page 36

Chapter 1: VC709 Evaluation Board Features
Table 1-10: PCIe Edge Connector Connections (Cont'd)
Net Name FPGA (U1) Pin
PCIE_RX4_N
PCIE_RX5_P
PCIE_RX5_N
PCIE_RX6_P
PCIE_RX6_N
PCIE_RX7_P
PCIE_RX7_N
PCIE_TX0_P
PCIE_TX0_N
PCIE_TX1_P
PCIE_TX1_N
PCIE_TX2_P
PCIE_TX2_N
PCIE_TX3_P
PCIE_TX3_N
PCIE_TX4_P
PCIE_TX4_N
PCIE_TX5_P
PCIE_TX5_N
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PCIe Edge
Connector (P1)
Pin Name
AD3 B34 PETn4
AE6 B37 PETp5
AE5 B38 PETn5
AF4 B41 PETp6
AF3 B42 PETn6
AG6 B45 PETp7
AG5 B46 PETn7
W2 A16 PERp0
W1 A17 PERn0
AA2 A21 PERp1
AA1 A22 PERn1
AC2 A25 PERp2
AC1 A26 PERn2
AE2 A29 PERp3
AE1 A30 PERn3
AG2 A35 PERp4
AG1 A36 PERn4
AH4 A39 PERp5
AH3 A40 PERn5
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Function
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
receive pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
Integrated Endpoint block
transmit pair
FFG1761 Placement
GTHE2_CHANNEL_X1Y19
GTHE2_CHANNEL_X1Y18
GTHE2_CHANNEL_X1Y18
GTHE2_CHANNEL_X1Y17
GTHE2_CHANNEL_X1Y17
GTHE2_CHANNEL_X1Y16
GTHE2_CHANNEL_X1Y16
GTHE2_CHANNEL_X1Y23
GTHE2_CHANNEL_X1Y23
GTHE2_CHANNEL_X1Y22
GTHE2_CHANNEL_X1Y22
GTHE2_CHANNEL_X1Y21
GTHE2_CHANNEL_X1Y21
GTHE2_CHANNEL_X1Y20
GTHE2_CHANNEL_X1Y20
GTHE2_CHANNEL_X1Y19
GTHE2_CHANNEL_X1Y19
GTHE2_CHANNEL_X1Y18
GTHE2_CHANNEL_X1Y18
VC709 Evaluation Board
UG887 (v1.2.1) March 11, 2014