Motorola MC68020 User Manual page 13

9/29/95
LIST OF ILLUSTRATIONS (Concluded)
Figure
Number
7-45 MC68020/EC020 Postinstruction Stack Frame................................................ 7-48
8-1 Concurrent Instruction Execution ..................................................................... 8-3
8-2 Instruction Execution for Instruction Timing Purposes ..................................... 8-3
8-3 Processor Activity for Example 1 ..................................................................... 8-5
8-4 Processor Activity for Example 2 ..................................................................... 8-6
8-5 Processor Activity for Example 3 ..................................................................... 8-7
8-6 Processor Activity for Example 4 ..................................................................... 8-8
9-1 32-Bit Data Bus Coprocessor Connection........................................................ 9-2
9-2 Chip Select Generation PAL ............................................................................ 9-3
9-3 Chip Select PAL Equations .............................................................................. 9-4
9-4 Bus Cycle Timing Diagram ............................................................................... 9-4
9-5 Example MC68020/EC020 Byte Select PAL System Configuration ................ 9-7
9-6 MC68020/EC020 Byte Select PAL Equations .................................................. 9-8
9-7 High-Resolution Clock Controller ..................................................................... 9-11
9-8 Alternate Clock Solution ................................................................................... 9-11
9-9 Access Time Computation Diagram ................................................................. 9-12
9-10 Module Descriptor Format ................................................................................ 9-15
9-11 Module Entry Word .......................................................................................... 9-15
9-12 Module Call Stack Frame ................................................................................. 9-16
9-13 Access Level Control Bus Registers ................................................................ 9-17
10-1 Drive Levels and Test Points for AC Specifications ....................................... 10-6
10-2 Clock Input Timing Diagram ........................................................................... 10-7
10-3 Read Cycle Timing Diagram .......................................................................... 10-11
10-4 Write Cycle Timing Diagram........................................................................... 10-12
10-5 Bus Arbitration Timing Diagram ..................................................................... 10-13
A-1 Bus Arbitration Circuit-MC68EC020 (Two-Wire) to DMA (Three-Wire) ......... A-1
MOTOROLA
SECTION 1: OVERVIEW
Title
M68020 USER'S MANUAL
UM Rev 1
Page
Number
xvii