Bus Arbitration Control (Mc68Ec020) - Motorola MC68020 User Manual

5.7.2.3 BUS ARBITRATION CONTROL (MC68EC020). The bus arbitration control unit in
the MC68EC020 is implemented with a finite state machine. As discussed previously, all
asynchronous inputs to the MC68EC020 are internally synchronized in a maximum of two
cycles of the processor clock.
As shown in Figure 5-48, the input signal labeled R is an internally synchronized version
of the BR signal. The BG output is labeled G, and the internal high-impedance control
signal is labeled T. If T is true, the address, data, and control buses are placed in the high-
impedance state after the next rising edge following the negation of AS and RMC. All
signals are shown in positive logic (active high), regardless of their true active voltage
level.
Figure 5-48. MC68EC020 Bus Arbitration State Diagram
MOTOROLA
R
GT
STATE1
X
R
GT
STATE 2
R
R—BUS REQUEST
G—BUS GRANT
T —THREE-STATE CONTROL TO BUS CONTROL LOGIC
X—DON'T CARE
M68020 USER'S MANUAL
R
GT
R
STATE 0
STATE 4
X
GT
STATE 3
STATE 5
R
X
GT
STATE 6
R
GT
R
GT
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