Motorola MC68020 User Manual page 79

State 0
MC68020—The read cycle starts in state 0 (S0). The processor asserts ECS, indicating
the beginning of an external cycle. If the cycle is the first external cycle of a read
operation, OCS is asserted simultaneously. During S0, the processor places a valid
address on A31–A0 and valid function codes on FC2–FC0. The function codes select
the address space for the cycle. The processor drives R/W high for a read cycle and
negates DBEN to disable the data buffers. SIZ0 and SIZ1 become valid, indicating the
number of bytes requested to be transferred.
MC68EC020—The read cycle starts in S0. During S0, the processor places a valid
address on A23–A0 and valid function codes on FC2–FC0. The function codes select
the address space for the cycle. The processor drives R/W high for a read cycle. SIZ0
and SIZ1 become valid, indicating the number of bytes requested to be transferred.
State 1
MC68020—One-half clock later in state 1 (S1), the processor asserts AS, indicating that
the address on the address bus is valid. The processor also asserts DS during S1. In
addition, the ECS (and OCS, if asserted) signal is negated during S1.
MC68EC020—One-half clock later in S1, the processor asserts AS, indicating that the
address on the address bus is valid. The processor also asserts DS during S1.
State 2
MC68020—During state 2 (S2), the processor asserts DBEN to enable external data
buffers. The selected device uses R/W, SIZ1–SIZ0, A1–A0, and DS to place its
information on the data bus. Any or all of the bytes (D31–D24, D23–D16, D15–D8, and
D7–D0) are selected by SIZ1–SIZ0 and A1–A0. Concurrently, the selected device
asserts DSACK1/DSACK0.
MC68EC020—During S2, the selected device uses R/W, SIZ1–SIZ0, A1–A0, and DS to
place its information on the data bus. Any or all of the bytes (D31–D24, D23–D16,
D15–D8, and D7–D0) are selected by SIZ1–SIZ0 and A1–A0. Concurrently, the
selected device asserts DSACK1/DSACK0.
State 3
MC68020/EC020—As long as at least one of the DSACK1/DSACK0 signals is
recognized by the end of S2 (meeting the asynchronous input setup time requirement),
data is latched on the next falling edge of the clock, and the cycle terminates. If
DSACK1/DSACK0 is not recognized by the start of state 3 (S3), the processor inserts
wait states instead of proceeding to states 4 and 5. To ensure that wait states are
inserted, both DSACK1 and D S A C K 0 must remain negated throughout the
asynchronous input setup and hold times around the end of S2. If wait states are
added, the processor continues to sample the DSACK1/DSACK0 signals on the falling
edges of the clock until an assertion is recognized.
MOTOROLA M68020 USER'S MANUAL 5- 31