Coprocessor Instruction Format - Motorola MC68020 User Manual

model of sequential, nonconcurrent instruction execution at the user level. Consequently,
the programmer can assume that the images of registers and memory affected by a given
instruction have been updated when the next instruction in the sequence accessing these
registers or memory locations is executed.
The M68000 coprocessor interface provides full support of all operations necessary for
nonconcurrent operation of the main processor and its associated coprocessors. Although
the M68000 coprocessor interface allows concurrency in coprocessor execution, the
coprocessor designer is responsible for implementing this concurrency while maintaining a
programming model based on sequential nonconcurrent instruction execution.
For example, if the coprocessor determines that instruction B does not use or alter
resources to be altered or used by instruction A, instruction B can be executed
concurrently (if the execution hardware is also available). Thus, the required instruction
interdependencies and sequences of the program are always respected. The MC68882
coprocessor offers concurrent instruction execution; whereas, the MC68881 coprocessor
does not. However, the MC68020/EC020 can execute instructions concurrently with
coprocessor instruction execution in the MC68881.

7.1.3 Coprocessor Instruction Format

The instruction set for a given coprocessor is defined by the design of that coprocessor.
When a coprocessor instruction is encountered in the main processor instruction stream,
the MC68020/EC020 hardware initiates communication with the coprocessor and
coordinates any interaction necessary to execute the instruction with the coprocessor. A
programmer needs to know only the instruction set and register set defined by the
coprocessor to use the functions provided by the coprocessor hardware.
The instruction set of an M68000 coprocessor uses a subset of the F-line operation words
in the M68000 instruction set. The operation word is the first word of any M68000 family
instruction. The F-line operation word contains ones in bits 15–12 (refer to Figure 7-1); the
remaining bits are coprocessor and instruction dependent. The F-line operation word may
be followed by as many extension words as are required to provide additional information
necessary for the execution of the coprocessor instruction.
15 14 13 12 11 9 8 6 5 0
1 1 1 1 CpID TYPE TYPE DEPENDENT
Figure 7-1. F-Line Coprocessor Instruction Operation Word
As shown in Figure 7-1, bits 11–9 of the F-line operation word encode the coprocessor
identification (CpID) field. The MC68020/EC020 uses the CpID field to indicate the
coprocessor to which the instruction applies. F-line operation words, in which the CpID is
zero, are not coprocessor instructions for the MC68020/EC020. Instructions with a CpID of
zero and a nonzero type field are unimplemented instructions that cause the
MOTOROLA M68020 USER'S MANUAL 7- 3