9/29/95
LIST OF ILLUSTRATIONS (Continued)
Figure
Number
5-24
Write Cycle Flowchart ...................................................................................... 5-33
5-25
Read-Write-Read Cycles-32-Bit Port ............................................................. 5-34
5-26
Byte and Word Write Cycles-32-Bit Port ........................................................ 5-35
5-27
Long-Word Operand Write-8-Bit Port ............................................................ 5-36
5-28
Long-Word Operand Write-16-Bit Port........................................................... 5-37
5-29
5-30
Byte Read-Modify-Write Cycle-32-Bit Port (TAS Instruction) ........................ 5-41
5-31
MC68020/EC020 CPU Space Address Encoding ............................................ 5-45
5-32
5-33
5-34
5-35
Breakpoint Acknowledge Cycle Flowchart ....................................................... 5-50
5-36
5-37
Bus Error without DSACK1/DSACK0 ............................................................. 5-57
5-38
5-39
Late Bus Error with DSACK1/DSACK0 .......................................................... 5-58
5-40
Late Retry......................................................................................................... 5-59
5-41
Halt Operation Timing ...................................................................................... 5-61
5-42
5-43
MC68020 Bus Arbitration Operation Timing for Single Request ...................... 5-65
5-44
MC68020 Bus Arbitration State Diagram ......................................................... 5-67
5-45
MC68020 Bus Arbitration Operation Timing-Bus Inactive ............................. 5-69
5-46
MC68EC020 Bus Arbitration Flowchart for Single Request ............................. 5-71
5-47
5-48
MC68EC020 Bus Arbitration State Diagram .................................................... 5-73
5-49
MC68EC020 Bus Arbitration Operation Timing-Bus Inactive ........................ 5-75
5-50
Interface for Three-Wire to Two-Wire Bus Arbitration ...................................... 5-76
5-51
5-52
6-1
Reset Operation Flowchart .............................................................................. 6-5
6-2
6-3
6-4
6-5
6-6
6-7
6-8
Special Status Word Format ............................................................................ 6-22
7-1
F-Line Coprocessor Instruction Operation Word.............................................. 7-3
7-2
Asynchronous Non-DMA M68000 Coprocessor Interface Signal Usage ......... 7-5
7-3
MC68020/EC020 CPU Space Address Encodings .......................................... 7-6
MOTOROLA
SECTION 1: OVERVIEW
Title
M68020 USER'S MANUAL
UM Rev 1
Page
Number
xv