Signal Index - Motorola MC68020 User Manual

Signal Name
Function Codes
Address Bus
MC68020
MC68EC020
Data Bus
Size
*
External Cycle Start
*
Operand Cycle Start
Read/Write
Read-Modify-Write Cycle
Address Strobe
Data Strobe
*
Data Buffer Enable
Data Transfer and Size
Acknowledge
Interrupt Priority Level
*
Interrupt Pending
Autovector
Bus Request
Bus Grant
*
Bus Grant Acknowledge
Reset
Halt
Bus Error
Cache Disable
Clock
Power Supply
Ground
*
This signal is implemented in the MC68020 and not implemented in the MC68EC020.
MOTOROLA
Table 3-1. Signal Index
Mnemonic
FC2–FC0 3-bit function code used to identify the address space of each bus cycle.
A31–A0 32-bit address bus
A23–A0 24-bit address bus
D31–D0 32-bit data bus used to transfer 8, 16, 24, or 32 bits of data per bus
cycle.
SIZ1, SIZ0 Indicates the number of bytes remaining to be transferred for this cycle.
These signals, together with A1 and A0, define the active sections of the
data bus.
ECS Provides an indication that a bus cycle is beginning.
OCS Identical operation to that of ECS except that OCS is asserted only during
the first bus cycle of an operand transfer.
R/ W Defines the bus transfer as a processor read or write.
RMC Provides an indicator that the current bus cycle is part of an indivisible
read-modify-write operation.
AS
Indicates that a valid address is on the bus.
DS Indicates that valid data is to be placed on the data bus by an external
device or has been placed on the data bus by the MC68020/EC020.
DBEN
Provides an enable signal for external data buffers.
DSACK1,
Bus response signals that indicate the requested data transfer operation
DSACK0 has completed. In addition, these two lines indicate the size of the
external bus port on a cycle-by-cycle basis and are used for
asynchronous transfers.
IPL2–IPL0 Provides an encoded interrupt level to the processor.
IPEND
Indicates that an interrupt is pending.
AVEC
Requests an autovector during an interrupt acknowledge cycle.
BR Indicates that an external device requires bus mastership.
BG Indicates that an external device may assume bus mastership.
BGACK Indicates that an external device has assumed bus mastership.
RESET
System reset.
HALT
Indicates that the processor should suspend bus activity or that the
processor has halted due to a double bus fault.
BERR
Indicates that an erroneous bus operation is being attempted.
CDIS
Statically disables the on-chip cache to assist emulator support.
CLK Clock input to the processor.
V Power supply.
CC
GND Ground connection.
M68020 USER'S MANUAL
Function
3- 3