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TABLE OF CONTENTS (Continued)
Paragraph
Number
3.12
3.13
Signal Summary...................................................................................... 3-8
4.1
4.2
Cache Reset ........................................................................................... 4-3
4.3
Cache Control ......................................................................................... 4-3
4.3.1
4.3.2
5.1
Bus Transfer Signals............................................................................... 5-1
5.1.1
Bus Control Signals ............................................................................. 5-2
5.1.2
Address Bus ........................................................................................ 5-3
5.1.3
Address Strobe .................................................................................... 5-3
5.1.4
Data Bus.............................................................................................. 5-3
5.1.5
Data Strobe ......................................................................................... 5-4
5.1.6
Data Buffer Enable .............................................................................. 5-4
5.1.7
5.2
5.2.1
Dynamic Bus Sizing ............................................................................ 5-5
5.2.2
Misaligned Operands........................................................................... 5-14
5.2.3
5.2.4
5.2.5
Cache Interactions .............................................................................. 5-22
5.2.6
Bus Operation ..................................................................................... 5-24
Synchronous Operation with DSACK1/DSACK0 ............................... 5-24
5.2.7
5.3
Data Transfer Cycles .............................................................................. 5-25
5.3.1
Read Cycle .......................................................................................... 5-26
5.3.2
Write Cycle .......................................................................................... 5-33
5.3.3
5.4
CPU Space Cycles ................................................................................. 5-44
5.4.1
5.4.1.1
5.4.1.2
5.4.1.3
5.4.2
5.4.3
5.5
5.5.1
Bus Errors ........................................................................................... 5-55
viii
SECTION 1: OVERVIEW
Title
Section 4
Section 5
M68020 USER'S MANUAL
UM Rev.1.0
Page
Number
MOTOROLA