Autovector Interrupt Acknowledge Cycle; Spurious Interrupt Cycle - Motorola MC68020 User Manual

5.4.1.2 AUTOVECTOR INTERRUPT ACKNOWLEDGE CYCLE. When the interrupting
device cannot supply a vector number, it requests an automatically generated vector or
autovector. Instead of placing a vector number on the data bus and asserting
DSACK1/DSACK0, the device asserts AVEC to terminate the cycle. The DSACK1/DSACK0
signals may not be asserted during an interrupt acknowledge cycle terminated by AVEC.
The vector number supplied in an autovector operation is derived from the interrupt level
of the current interrupt. When AVEC is asserted instead of DSACK1/DSACK0 during an
interrupt acknowledge cycle, the MC68020/EC020 ignores the state of the data bus and
internally generates the vector number, the sum of the interrupt level plus 24 ($18). Seven
distinct autovectors, which correspond to the seven levels of interrupt available with IPL2–
IPL0, can be used. Figure 5-34 shows the timing for an autovector operation.
5.4.1.3 SPURIOUS INTERRUPT CYCLE. When a device does not respond to an interrupt
acknowledge cycle with AVEC or DSACK1/DSACK0, the external logic typically returns
BERR. In this case, the MC68020/EC020 automatically generates 24, the spurious
interrupt vector number. If HALT is also asserted, the processor retries the cycle.
5-48 M68020 USER'S MANUAL MOTOROLA