Initial Reset Operation Timing - Motorola MC68020 User Manual

CLK
+5 V
V CC
RESET
BUS
CYCLES
BUS STATE UNKNOWN
Resetting the processor causes any bus cycle in progress to terminate as if
DSACK1/DSACK0 or BERR had been asserted. In addition, the processor initializes
registers appropriately for a reset exception. Exception processing for a reset operation is
described in Section 6 Exception Processing.
When a RESET instruction is executed, the processor drives the RESET signal for 512
clock cycles. In this case, the processor resets the external devices of the system, and the
internal registers of the processor are unaffected. The external devices connected to the
RESET signal are reset at the completion of the RESET instruction. An external RESET
signal that is asserted to the processor during execution of a RESET instruction must
extend beyond the reset period of the instruction by at least eight clock cycles to reset the
processor. Figure 5-52 shows the timing information for the RESET instruction.
MOTOROLA
Figure 5-51. Initial Reset Operation Timing
M68020 USER'S MANUAL
t ≥ 520 CLOCKS
t < 4 CLOCKS
ENTIRE BUS
THREE-
STATED
4 CLOCKS
ALL CONTROL SIGNALS ISP
NEGATED, DATA BUS IN READ
READ MODE, ADDRESS STARTS
BUS DRIVEN
5- 77