Privilege Violations; Cptrapcc Instruction Traps; Trace Exceptions - Motorola MC68020 User Manual

counter field of the saved stack frame to point to the next instruction operation word and
executes the RTE instruction. The MC68020/EC020 then executes the instruction
following the instruction that was emulated.
The exception handler should also check the copy of the SR on the stack to determine
whether tracing is enabled. If tracing is enabled, the trace exception processing should
also be emulated. Refer to Section 6 Exception Processing for additional information.
7.5.2.3 PRIVILEGE VIOLATIONS. Privilege violations can result from the cpSAVE and
cpRESTORE instructions and from the supervisor check coprocessor response primitive.
The MC68020/EC020 initiates privilege violation exception processing if it attempts to
execute either the cpSAVE or cpRESTORE instruction when it is in the user state (S = 0
in the SR). The main processor initiates this exception processing prior to any
communication with the coprocessor associated with the cpSAVE or cpRESTORE
instructions.
If the main processor is executing a coprocessor instruction in the user state when it reads
the supervisor check primitive, it aborts the coprocessor instruction in progress by writing
an abort mask to the control CIR (refer to 7.3.2 Control CIR). The main processor then
performs privilege violation exception processing.
If a privilege violation occurs, the main processor initiates exception processing using the
four-word preinstruction stack frame (refer to Figure 7-41) and the privilege violation
exception vector number 8. Thus, if the exception handler does not modify the stack
frame, the main processor attempts to restart the instruction during which the exception
occurred after it executes an RTE to return from the handler.
7.5.2.4 cpTRAPcc INSTRUCTION TRAPS. If, during the execution of a cpTRAPcc
instruction, the coprocessor returns the TRUE condition indicator to the main processor
with a null primitive, the main processor initiates trap exception processing. The main
processor uses the six-word postinstruction exception stack frame (refer to Figure 7-45)
and the trap exception vector number 7. The scanPC field of this stack frame contains the
address of the instruction following the cpTRAPcc instruction. The processing associated
with the cpTRAPcc instruction can then proceed, and the exception handler can locate
any immediate operand words encoded in the cpTRAPcc instruction using the information
contained in the six-word stack frame. If the exception handler does not modify the stack
frame, the main processor executes the instruction following the cpTRAPcc instruction
after it executes an RTE instruction to exit from the handler.
7.5.2.5 TRACE EXCEPTIONS. The MC68020/EC020 supports two modes of instruction
tracing, as discussed in Section 6 Exception Processing. In the trace on instruction
execution mode, the MC68020/EC020 takes a trace exception after completing each
instruction. In the trace on change of flow mode, the MC68020/EC020 takes a trace
exception after each instruction that alters the SR or places an address other than the
address of the next instruction in the PC.
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