User Gpio Interface; System Management Bus (Smbus); Table 3-10. User Gpio Interface Pin/Signal Descriptions (J20); Table 3-11. Smbus Reserved Addresses - ADLINK Technology CoreModule 730 Reference Manual

Chapter 3

User GPIO Interface

The CoreModule 730 provides GPIO pins for customer use, and the signals are routed to header J20 which
uses 10 pins with odd/even (1,2) pin sequence and 0.049" (2mm) pitch. An example of how to use the GPIO
pins resides in the Miscellaneous Source Code Examples on the CoreModule 730 Support QuickDrive

Table 3-10. User GPIO Interface Pin/Signal Descriptions (J20)

Pin # Signal
1 H8S_GPI0
2 H8S_GPO0
3 H8S_GPI1
4 H8S_GPO1
5 H8S_GPI2
6 H8S_GPO2
7 H8S_GPI3
8 H8S_GPO3
9 GND
10 GND
Note: The shaded areas denote ground.

System Management Bus (SMBus)

The SCH chip contains a host SMBus port. The host port allows the CPU access to the SMBus slaves
through header J27. The SMBus slaves include the SODIMM EPROM, Ethernet controller, CPU
Temperature Sensor, Clock Buffer, and the Clock Generator.
corresponding reserved binary addresses on the SMBus.
row, 0.049" (2 mm) pitch on the external SMBus header (J27).

Table 3-11. SMBus Reserved Addresses

Component
SODIMM EPROM
Clock Generator
Clock Buffer
CPU Temperature Sensor

Table 3-12. SMBus Pin Signals (J27)

Pin # Signal
1 SMB_CLK
2 GND
3 SMB_DATA
4 VSM
5 /SMB_ALERT*
Note: The shaded areas denote power or ground. The signals marked with * indicate Negative true logic.
24
Description
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
Ground
Ground
Table 3-11
Table 3-12
Address Binary
1010,000x
1101,001x
1101,110x
1001,100x
Description
SMBus Clock
Ground
SMBus Data
+3.3V standby voltage
SMBus Alert
Reference Manual
lists the device names and
lists the SMBus pin signals on 5 pins, 1
b
b
b
b
Hardware
TM
.
CoreModule 730