Power Interface; User Gpio Interface; Table 3-12. Power Interface Pin Signals (J19); Table 3-13. User Gpio Interface Pin Signals (J3) - ADLINK Technology CoreModule 720 Reference Manual

Chapter 3

Power Interface

The CoreModule 720 requires one +5 volt DC power source and provides a shrouded 10-pin, right-angle
header with 2 rows, odd/even pin sequence (1, 2), and 0.100" (2.54mm) pitch. If the +5VDC power drops
below ~4.65V, a low voltage reset is triggered, resetting the system.
The power input header (J19) supplies the following voltage and ground directly to the module:
•
5.0VDC +/- 5%

Table 3-12. Power Interface Pin Signals (J19)

Pin Signal
1 GND
2 +5V
3 GND
4 +12V
5 GND
6 +3.3V_PCI
7 GND
8 +5V
9 GND
10 +5V
Note: The shaded table cells denote power or ground.

User GPIO Interface

The CoreModule 720 provides GPIO pins for customer use, routing the signals from the PCH EG20T
chipset to the J3 header. An example test application and source code reside in each BSP directory of the
CoreModule 720 Support Software QuickDrive.
For instructions on using the example applications, refer to the GPIO Readme in each BSP directory of the
QuickDrive. For more information about the GPIO pin operation, refer to the PCH EG20T datasheet at:
http://download.intel.com/embedded/chipsets/datasheet/324211.pdf
Table 3-13 describes the pin signals of the GPIO interface, which consists of a 10-pin header with 2 rows,
odd/even pin sequence (1, 2), and 0.079" (2mm) pitch.

Table 3-13. User GPIO Interface Pin Signals (J3)

Pin # Signal from PCH
1 GPIO0
2 GPIO4
3 GPIO1
4 GPIO5
5 GPIO2
6 GPIO6
7 GPIO3
8 GPIO7
9 GND
10 GND
Note: The shaded table cells denote ground.
CoreModule 720
Descriptions
Ground
+5 Volts
Ground
+12 Volts routed to PC/104, PC/104-Plus, and LVDS interfaces
Ground
+3.3 Volts routed to PCI
Ground
+5 Volts
Ground
+5 Volts
Description
User defined
User defined
User defined
User defined
User defined
User defined
User defined
User defined
Ground
Ground
Reference Manual
Hardware
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