Figure 1. Block Diagram - STMicroelectronics STM32F050G6 Manual

STM32F050xx
Figure 1. Block diagram
SWCLK
Serial Wire
SWDAT
Debug
as AF
CORTEX-M0 CPU
f HCLK = 48 MHz
NVIC
NVIC
5 channels
GPIO port A
PA[15:0]
PB[15:0]
GPIO port B
GPIO port C
PC[15:13]
PF[7:6, 1:0] GPIO port F
EXT.IT
39 AF
WKUP
MOSI/SD,
MISO/MCK,
SPI1/I2S1
SCK/CK,
NSS/WS as AF
SYSCFG IF
Temp sensor
10
12-bit ADC1
ADC_IN
V
DDA
V
SSA
@V
DDA
GP DMA
AHB
APB
IF
Doc ID 023079 Rev 3
V
FLASH
32 KB
32 bits
POR
Reset
SRAM
@V
4 KB DDA
RC HS 14 MHz
RC HS 8 MHz
RC LS
PLL
AHBPCLK
APBPCLK
RESET
ADCCLK
CECCLK
& CLOCK
CONTROL USARTCLK
HCLK
FCLK
CRC
WWDG
DBGMCU
POWER
DD18
V
DD
VOLT. REG.
3.3 V T O 1.8 V
V
SS
@V
DD
SUPPLY
NRST
SUPERVISION
V
DDA
POR / PDR
Int
V
DD
PVD
@V
DDA
@V
DD
OSCIN - PF0
XTAL OSC
OSCOUT - PF1
4-32 MHz
IWDG
Power
Controller
V
BAT
@VSW
OSC32_IN
XTAL 32kHz
OSC32_OUT
Backup
TAMPER-RTC
RTC
reg
(ALARM OUT)
RTC interface
4 channels
TIMER 1
3 compl. channels
BRK, ETR input as AF
TIMER 2 4 ch, ETR as AF
TIMER 3
4 ch, ETR as AF
TIMER 14
1 channel as AF
1 channel,
TIMER 16
1 compl, BRK as AF
1 channel,
TIMER 17
1 compl, BRK as AF
IR_OUT as AF
RX,TX, CTS, RTS,
USART1
CK as AF
SCL,SDA,SMBal
I2C1 (20 mA for FM+)
as AF
Description
=2 to 3.6V
=1.65 V to 3.6 V
MS30246V2
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