STMicroelectronics STM32F050G6 Manual page 79

STM32F050xx
Figure 27. SPI timing diagram - slave mode and CPHA = 1
NSS input
t SU(NSS)
CPHA=1
CPOL=0
t w(SCKH)
CPHA=1
t w(SCKL)
CPOL=1
t a(SO)
MISO
OUT P UT
MOSI
I NPUT
1. Measurement points are done at CMOS levels: 0.3V
Figure 28. SPI timing diagram - master mode
High
NSS input
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
t su(MI)
MISO
INP UT
MOSI
OUTUT
1. Measurement points are done at CMOS levels: 0.3V
t v(SO)
MS B O UT
t su(SI)
t h(SI)
M SB IN
t c(SCK)
t w(SCKH)
t w(SCKL)
MS BIN
t h(MI)
M SB OUT
t v(MO)
Doc ID 023079 Rev 3
(1)
t c(SCK)
t h(SO)
BI T6 OUT
B I T1 IN
and 0.7V
.
DD DD
(1)
BI T6 IN
B I T1 OUT
t h(MO)
and 0.7V
.
DD DD
Electrical characteristics
t h(NSS)
t r(SCK)
t dis(SO)
t f(SCK)
LSB OUT
LSB IN
ai14135
t r(SCK)
t f(SCK)
LSB IN
LSB OUT
ai14136
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