Nrst Pin Characteristics; Table 48. Nrst Pin Characteristics; Figure 21. I/O Ac Characteristics Definition; Figure 22. Recommended Nrst Pin Protection - STMicroelectronics STM32F050G6 Manual

Electrical characteristics

Figure 21. I/O AC characteristics definition

6.3.14

NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, R
Unless otherwise specified, the parameters given in
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 15.
Table 48.
Symbol
V
IL(NRST)
V
IH(NRST)
V
hys(NRST)
R
PU
V
F(NRST)
V
NF(NRST)
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum

Figure 22. Recommended NRST pin protection

1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the V
Table 48. Otherwise the reset will not be taken into account by the device.
70/98
t r(I O)out
EXT ERNAL
OUTPUT
ON 50pF
Maximum frequency is achieved if (t r + t f ) 2/3)T and if the duty cycle is (45-55%)
(see Table 45).
PU
NRST pin characteristics
Parameter
(1)
NRST input low level voltage
(1)
NRST input high level voltage
NRST Schmitt trigger voltage
hysteresis
Weak pull-up equivalent resistor
(1)
NRST input filtered pulse
(1)
NRST input not filtered pulse
External
(1)
reset circuit
NRST
0.1 μF
Doc ID 023079 Rev 3
90% 10%
50%
10%
T
when loaded by 50pF
Table 48
Conditions
(2)
V
IN
.
(~10% order)
V DD
R PU
(2)
50%
90%
t r(I O)out
are derived from tests
Min Typ
–0.3 -
2 -
- 200

V 25 40
SS
- -
300 -
Internal Reset
Filter
MS19878V1
max level specified in
IL(NRST)
STM32F050xx
ai14131
Max Unit
0.8
V
V +0.3
DD
- mV
55 k
100 ns
- ns