Figure 29. I2S Slave Timing Diagram (Philips Protocol); Figure 30. I2S Master Timing Diagram (Philips Protocol) - STMicroelectronics STM32F050G6 Manual

STM32F050xx

Figure 29. I2S slave timing diagram (Philips protocol)

CPOL = 0
CPOL = 1
WS input
SD transmit
SD receive
1. Measurement points are done at CMOS levels: 0.3 × V
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.

Figure 30. I2S master timing diagram (Philips protocol)

CPOL = 0
CPOL = 1
WS output
SD transmit
SD receive
1. Data based on characterization results, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
t w(CKH)
t su(WS)
LSB transmit
t su(SD_SR)
LSB receive
t c(CK)
t w(CKH)
t v(WS)
LSB transmit
t su(SD_MR)
LSB receive
Doc ID 023079 Rev 3
t c(CK)
t w(CKL)
(2)
MSB transmit
(2)
MSB receive
and 0.7 × V
DD DD
t f(CK)
t w(CKL)
(2)
MSB transmit
t h(SD_MR)
(2)
MSB receive
Electrical characteristics
t h(WS)
t v(SD_ST) t h(SD_ST)
Bitn transmit LSB transmit
t h(SD_SR)
Bitn receive LSB receive
.
t r(CK)
t h(WS)
t v(SD_MT) t h(SD_MT)
Bitn transmit LSB transmit
Bitn receive LSB receive
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