Clocks And Startup; Figure 2. Clock Tree - STMicroelectronics STM32F050G6 Manual

STM32F050xx
3.6

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the application to configure the frequency of the AHB and the APB
domains. The maximum frequency of the AHB and the APB domains is 48 MHz.
Figure 2. Clock tree
8 MHz
HSI RC
PLLSRC
/1,2,
3,..16
OSC_OUT
4-32 MHz
HSE OSC
OSC_IN
OSC32_IN
LSE OSC
32.768kHz
OSC32_OUT
LSI RC
40kHz
Main clock
output
MCO
HSI
/2
SW
PLLMUL
HSI
PLL
PLLCLK
prescaler
x2,x3,..
/1,2,..512
x16
HSE
SYSCLK
CSS
14 MHz
HSI14 RC
/32
RTCCLK
LSE
RTCSEL[1:0]
LSI
/2 PLLCLK
HSI
HSI14
HSE
SYSCLK
MCO
Doc ID 023079 Rev 3
HSI
SYSCLK
HCLK
/8
AHB APB
AHB
prescaler
/1,2,4,8,16
If (APB1 prescaler
=1) x1 else x2
ADC
Prescaler
/2,4
HSI14
PCLK
SYSCLK
HSI
to RTC
LSE
to IWWDG
IWWDGCLK
Functional overview
FLITFCLK
to Flash programming interface
to I2C1
to I2S1
to AHB bus, core,
memory and DMA
to cortex System timer
FHCLK Cortex free running clock
PCLK
to APB peripherals
to TIM1,2,3,
14,16,17
to ADC
14 MHz max
to USART1
MS30247V1
15/98