STMicroelectronics STM32F050G6 Manual page 65

STM32F050xx
Table 45. I/O static characteristics (continued)
Symbol Parameter
I Input leakage current
lkg
Weak pull-up equivalent
R
(4)
PU
resistor
Weak pull-down
R
PD
equivalent resistor
C I/O pin capacitance
IO
1. To sustain a voltage higher than V
2. Hysteresis voltage between Schmitt trigger switching levels. Data based on characterization, not tested in production.
3. Leakage could be higher than max. if negative current is injected on adjacent pins.
4. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in
in Figure 19
Conditions

V V
SS IN
I/O TC, FT and FTf

V V
SS IN
 
2 V V V
DD DDA
I/O TTa used in digital
mode
V
=
IN
I/O FT and FTf
(3)
V 3.6 V
=
IN

2 V V
DD
V
DDA =
I/O TTa used in digital
mode

V V
SS IN
 
2 V V V
DD DDA
I/O TTa used in analog
mode

V V
IN

V V
(4)
IN
+0.3 the internal pull-up/pull-down resistors must be disabled.
DD
to the series resistance is minimum
and Figure 20 for 5 V tolerant I/Os.
Doc ID 023079 Rev 3
Min

V
DD
-

V
DD

3.6 V
-
5 V
-
,

V
IN
3.6 V -

V
DDA

3.6 V
-
25
SS
25
DD
-
.
(~10% order)
Figure 17
Electrical characteristics
Typ Max
1
-
1
-
- 10
- 1
2
-
40 55
40 55
5 -
and Figure 18 for standard I/Os, and
Unit
µA
k
k
pF
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