Table 60. I 2 S Characteristics - STMicroelectronics STM32F050G6 Manual

Electrical characteristics
2
Table 60. I S characteristics
Symbol
f
CK 2
I S clock frequency
1/t
c(CK)
2
t I S clock rise time
r(CK)
2
t I S clock fall time
f(CK)
(1)
t I2S clock high time
w(CKH)
(1)
t I2S clock low time
w(CKL)
(1)
t WS valid time
v(WS)
(1)
t WS hold time
h(WS)
(1)
t WS setup time
su(WS)
(1)
t WS hold time
h(WS)
I2S slave input clock duty
DuCy(SCK)
cycle
(1)
t Data input setup time
su(SD_MR)
(1)
t Data input setup time
su(SD_SR)
(1)(2)
t
h(SD_MR)
Data input hold time
(1)(2)
t
h(SD_SR)
(1)(2)
t Data output valid time
v(SD_ST)
(1)
t Data output hold time
h(SD_ST)
(1)(2)
t Data output valid time
v(SD_MT)
(1)
t Data output hold time
h(SD_MT)
1. Data based on design simulation and/or characterization results, not tested in production.
2. Depends on f . For example, if f
PCLK
80/98
Parameter
Master mode (data: 16 bits, Audio
frequency = 48 kHz)
Slave mode
Capacitive load C
Master f
frequency = 48 kHz
Master mode
Master mode
Slave mode
Slave mode
Slave mode
Master receiver
Slave receiver
Master receiver
Slave receiver
Slave transmitter (after enable
edge)
Slave transmitter (after enable
edge)
Master transmitter (after enable
edge)
Master transmitter (after enable
edge)
=8 MHz, then T
PCLK
Doc ID 023079 Rev 3
Conditions
= 15 pF
L
= 16 MHz, audio
PCLK
= 1/f =125 ns.
PCLK PLCLK
STM32F050xx
Min Max Unit
1.597 1.601
MHz
0 6.5
- 10
- 12
306 -
312 -
2 -
2 -
7 -
0 -
25 75
6 -
2 -
4 -
0.5 -
- 20
13 -
- 4
0 -
ns
%
ns