Figure 26. Spi Timing Diagram - Slave Mode And Cpha = 0 - STMicroelectronics STM32F050G6 Manual

Electrical characteristics
Table 59. SPI characteristics (continued)
Symbol Parameter
(1)
t NSS setup time
su(NSS)
(1)
t NSS hold time
h(NSS)
(1)
t
w(SCKH)
SCK high and low time
(1)
t
w(SCKL)
(1)
t
su(MI)
Data input setup time
(1)
t
su(SI)
(1)
t
h(MI)
Data input hold time
(1)
t
h(SI)
(1)(2)
t Data output access time
a(SO)
(1)(3)
t Data output disable time
dis(SO)
(1)
t Data output valid time
v(SO)
(1)
t Data output valid time
v(MO)
(1)
t
h(SO)
Data output hold time
(1)
t
h(MO)
SPI slave input clock duty
DuCy(SCK)
cycle
1. Data based on characterization results, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z

Figure 26. SPI timing diagram - slave mode and CPHA = 0

NSS input
CPHA= 0
CPOL=0
t w(SCKH)
CPHA= 0
t w(SCKL)
CPOL=1
t a(SO)
MISO
OUT P UT
t su(SI)
MOSI
I NPUT
78/98
Slave mode
Slave mode
Master mode, f
presc = 4
Master mode
Slave mode
Master mode
Slave mode
Slave mode, f
Slave mode
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode
t c(SCK)
t SU(NSS)
t v(SO)
MS B O UT
M SB IN
t h(SI)
Doc ID 023079 Rev 3
Conditions
= 36 MHz,
PCLK
= 20 MHz
PCLK
t h(SO)
BI T6 OUT
B I T1 IN
STM32F050xx
Min Max
4Tpclk -
2Tpclk + 10 -
Tpclk/2 -2 Tpclk/2 + 1
4 -
5 -
4 -
5 -
0 3Tpclk
0 18
- 22.5
- 6
11.5 -
2 -
25 75
t h(NSS)
t r(SCK)
t dis(SO)
t f(SCK)
LSB OUT
LSB IN
Unit
ns
%
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