Sony BVP-550 Maintenance Manual page 603

TA8129Z(TOSHIBA)
FM IF SYSTEM (DIFFERENTIAL PEAK DETECT)
— SIDE VIEW —
GND GND
1 2 3 4 5 6 7 8 9 10 11
F DET
METER MUTE
IF AMP
DRIVE DRIVE
STATION
DET
AF AMP
1 2 3 4 5 6 7 9 10 11
TC4S01F(TOSHIBA)CHIP PACKAGE
TC7S02FU(TOSHIBA)CHIP PACKAGE
TC7SH02FU(TOSHIBA)CHIP PACKAGE
C-MOS 2-INPUT NOR GATE
(SCALE 6/1)
—TOP VIEW—
1
A A
4
1 5 V
DD
Y =
2
B B
2
Y = A + B = A • B
GND 3 4
A B Y
0 0 1
0 1 0
1 0 0
0 ; LOW LEVEL
1 1 0
1 ; HIGH LEVEL
V
TYPE DD
+3 to +18V
4S01F
7S02F
+2 to +6V
7S02FU
7SH02FU
TC4S11F(TOSHIBA)CHIP PACKAGE
TC7S00FU(TOSHIBA)CHIP PACKAGE
C-MOS 2-INPUT NAND GATE
— TOP VIEW —
(SCALE 6/1)
2
1 5 V A A
DD
4
Y =
1
B
B
2
Y = A • B = A + B
GND 3 4
A B Y
0 0 1
0 1 1
1 0 1
0 ; LOW LEVEL
1 1 0
1 ; HIGH LEVEL
TYPE V
DD
7S00F
+2 to +6 V
7S00FU
4S11F
+3 to +18 V
4SU11F
+2 to +5.5 V
7SH00FU
BVP-550
V
CC
(+16 V)
12 13 14 15 16
LPF
REG
PEAK DET
12 13 14 15 16
Y
Y
TC4S30F(TOSHIBA)CHIP PACKAGE
TC7S86FU(TOSHIBA)CHIP PACKAGE
C-MOS 2-INPUT EXCLUSIVE OR GATE
(SCALE 6/1)
—TOP VIEW—
2
A
4
1
5 V
DD 1
B
2
GND 3 4
Y = A • B + A • B
A B Y
0 0 0
0 1 1
1 0 1
0 ; LOW LEVEL
1 1 0
1 ; HIGH LEVEL
TYPE
7S86FU
7S86F
4S30F
TC4S69F(TOSHIBA)CHIP PACKAGE
TC4SU69F(TOSHIBA)CHIP PACKAGE
TC7S04FU(TOSHIBA)CHIP PACKAGE
TC7SH04FU(TOSHIBA)CHIP PACKAGE
C-MOS INVERTER
(SCALE 6/1)
—TOP VIEW—
1
5 V 2 4
DD
A A
Y =
2
Y = A
GND 3 4
A Y
0 1
1 0
TYPE V 0 ; LOW LEVEL
DD
1 ; HIGH LEVEL
7S04F
7SU04F +2 to +6V
7SU04FU
4S69F
+3 to +18V
4SU69F
7SH04FU +2 to +5.5V
TC4S71F(TOSHIBA)CHIP PACKAGE
TC7S32FU(TOSHIBA)CHIP PACKAGE
TC7SH32FU(TOSHIBA)CHIP PACKAGE
C-MOS 2-INPUT OR GATE
(SCALE 6/1)
—TOP VIEW—
2
A
4
1 5 V
DD
1
B
2
GND 3 4
Y = A + B = A • B
A B Y
0 0 0
0 1 1
1 0 1
0 ; LOW LEVEL
1 1 1
1 ; HIGH LEVEL
TYPE
7S32F
7S32FU
4S71F
7SH32FU
Y
V
DD
+2 to +6V
+3 to +18V
Y
A
Y
Y =
B
V
DD
+2 to +6V
+3 to +18V
–2 to +5.5V
6-21
IC