Sony BVP-550 Maintenance Manual page 371

CXA1486Q (SONY)
VIDEO AMPLIFIER FOR VIDEO CAMERA
- TOP VIEW -
PIN
No.
25 16
26 V 15 1
CC
27 14 2
28 V I GND2 13 3
CC
29 12 4
30 11 5
31 10 6
32 9 7
8
9
10
11
12
13
14
15
16
24 23
INPUT
BLACK1 LPFC1
12 11
BLACK1, 2 ; FOR CLAMP DC COMPENSATION
BLKG FLT DET
26
BLKG ; BLANKING SIGNAL
G CTRL
14 29
BLK SHAD ; BLACK SHADING CORRECTION SIGNAL
ZERO LPF C2
2
CLP PLS1, 2 ; CLAMP PULSE
W SHAD
27
F COMP ; FLARE COMPENSATION SIGNAL
F COMP
FB REF ; OUTPUT 2 INVERT AMPLIFY DC ADJUST
30 31
G CTRL ; WHITE BALANCE GAIN CONTROL
BLACK2 CLP C1
18
GS1, 2 ; GAIN SELECT
SIG IN
16 11
KNEE PT ; KNEE POINT
BLK SHAD FLR DET
KNEE SW ; 1/4, 1/5 KNEE SELECT
19 25
(4.5V=1/4 KNEE, 0V=1/5 KNEE)
GS2 CLP C2
20
OUT SW ; OUTPUT 3 AMPLIFY SELECT
GS1
21
SIG IN
; SIGNAL INPUT
CLP PLS1
32
W SHAD ; WHITE SHADING SIGNAL
CLP PLS2
ZERO ; VARIABLE GAIN AMPLIFY ZERO POINT ADJUST
4 7
FB REF SIG OUT
9
OUTPUT
KNEE PT
CLP C1, C2 ; FOR CLAMP CAPACITANCE
1
FLR DET ; FLARE DETECT
OUT SW
10
LPF C1, C2 ; CONNECT CAPACITANCE FOR LPF
KNEE SW
SIG OUT ; SIGNAL OUTPUT
19, 20
GS1,2
21
CLP PLS1
24
BLACK1
23
LPF C1
G
12
BLKG BLKG
26
G CTRL
14
ZERO WBAL
2
W SHAD
27
F COMP
25
CLP C2
32
CLP PLS2
30
BLACK2
1/4 KNEE
1/5 KNEE
0dB
4
FB REF
4dB
0dB
1
OUT SW
BVP-550
V , V I, DR V , = (+5V)
CC CC CC
V , V I, DR V , = (-2.5 to -5.5V)
EE EE EE
PIN
I/O SIGNAL I/O SIGNAL
No.
I OUT SW 17 – GND1
I W SHAD 18 I SIG IN
– GND I 19 I GS2
I FB REF 20 I GS1
– V I 21 I CLP PLS1
EE
– DR V 22 – V
EE EE
O SIG OUT 23 O LPF C1
– DR V 24 I BLACK1
CC
I KNEE PT 25 O CLP C2
I KNEE SW 26 I G CTRL
O FLR DET 27 I
F COMP
I BLKG 28 – V I
CC
– GND2 29 O LPF C2
I ZERO 30 I BLACK2
– V 31 O CLP C1
CC
I BLK SHAD 32 I CLP PLS2
31
CLP C1
18
SIG IN
16
BLK SHAD
11
2dB FLR DET
29
LPF C2
9
KNEE PT
10
KNEE SW
8
DR V
DD
7
SIG OUT
DR
6
DR V
EE
CXD1171M(SONY)FLAT PACKAGE
C-MOS 8-BIT D/A CONVERTER
— TOP VIEW —
1
D. V
DD
D0 1 24
IN
2
(+5 V)
3
D. V
DD
D1 2 23
IN
4
(+5 V)
5
A. V
DD
D2 3 22
IN
6
(+5 V)
7
D3 4 21 IO
IN OUT
8
12
D4 5 20 IO
IN OUT
9
A. V
DD 16
D5 6 19
IN
(+5 V)
15
A. V
DD
D6 7 18
IN
(+5 V)
D7 8 17 VG
IN OUT
CK
BLK 9 16 VREF
IN IN
BLK
D0 - 7
10 D. GND 15 IREF
IN
IO
IO
VB 11 A. GND 14
IN
IREF
VB, VG
VREF
CK 12 13
IN B. GND
1 2 2 2
D0
D1 2
D2
3 - 5 3
– DECODER
LATCHES
D4
D5
6 - 8 3
– DECODER
D7
9
BLK
16
VREF +
15
–
IREF
11
VB
12 CLOCK
CK
GENERATOR
20
D0 IO
21
D1 IO
D2
D3
D4
D5
D6
D7
BLK
VREF
IREF
VB VG
11 17
; CLOCK INPUT
; BLANKING PULSE INPUT
; DIGITAL DATA INPUT
; CURRENT OUTPUT
; INVERT CURRENT OUTPUT
; CURRENT REFERENCE INPUT
; FOR CAPACITOR
; VOLTAGE REFERENCE INPUT
2
20
6MSB'S 2LSB'S IO
CURRENT CURRENT
21
CELLS CELLS
IO
17
VG
CURRENT
CELLS
FOR FULL
SCALE
6-7
IC