Sony BVP-550 Maintenance Manual page 590

IC
CXD2307R(SONY)FLAT PACKAGE
C-MOS 10-BIT 50MSPS RGB 3CHANNEL D/A CONVERTER
— TOP VIEW —
49 A V (GND)
SS
50
51
52 A V
DD (+7 V)
53 A V
DD (+7 V)
54
55
56 A V
DD (+7 V)
57 A V
DD (+7 V)
58
59
60 A V
DD (+7 V)
61 A V
DD (+7 V)
62 D V
DD (+7 V)
63
64
PIN PIN PIN
I/O SIGNAL I/O SIGNAL
No. No. No.
1 I R2 17 I G8 33
2 I R3 18 I G9 34
3 I R4 19 I B0 (LSB) 35
4 I R5 20 I B1 36
5 I R6 21 I B2 37
6 I R7 22 I B3 38
7 I R8 23 I B4 39
8 I R9 24 I B5 40
9 I G0 (LSB) 25 I B6 41
10 I G1 26 I B7 42
11 I G2 27 I B8 43
12 I G3 28 I B9 44
13 I G4 29 I BLK 45
14 I G5 30 I CE 46
15 I G6 31 I RCK 47
16 I G7 32 I GCK 48
63
R0
(LSB)
64
R1
1
R2
2
R3
3
R4
4
DECODER LATCHES
R5
5
R6
6
R7
7
R8 DECODER
8
R9
9
G0
(LSB)
10
G1
11
G2
12
G3
13
G4
14
LATCHES
G5 DECODER
15
G6
16
G7
17
G8 DECODER
18
G9
19
B0
(LSB)
20
B1
21
B2
22
B3
23
B4
24
B5 DECODER LATCHES
25
B6
26
B7
27
B8 DECODER
28
B9
29
BLK
30
CE
6-8
63
R0
64
R1
1
R2
32
2
R3 GO
31
3
R4 GO
30 4
R5
29 5
R6
28 6
R7
27
7
R8
26
8
R9
25
24
9
G0
23
10
G1
22
11
G2
21
12
G3
20
13
G4
19
14
G5
18
15
G6
17
16
G7
17
G8
18
G9
19
B0
20
B1
PIN
21
I/O SIGNAL I/O SIGNAL
B2
No.
22
B3
I BCK 49 — AV
SS
23
B4
— DV 50 O RO
SS
24
B5
O VB 51 O RO
25
B6
— AV 52 — AV
SS DD
26
B7
I IRR 53 — AV
DD
27
B8
I IRG 54 O GO
28
B9
I IRB 55 O GO
ROR
I VRR 56 — AV
DD
31
RCK ROG
I VRG 57 — AV
DD
32
GCK ROB
I VRB 58 O BO
33
BCK
I ROR 59 O BO
37
IRR VGR
I VGR 60 — AV
DD
38
IRG VGG
I ROG 61 — AV
DD
39
IRB VGB
I VGG 62 — DV
DD
40
VRR
I ROB 63 I R0 (LSB)
41
VRG
I VGB 64 I R1
42
VRB
BLK CE
29 30
4LSB' S
CURRENT
CELLS
6LSB' S
CURRENT
CELLS
CLOCK
GENERATOR
–
+
CURRENT CELLS
(FOR FULL SCALE)
4LSB' S
CURRENT
CELLS
6LSB' S
CURRENT
CELLS
CLOCK
GENERATOR
–
+
CURRENT CELLS
(FOR FULL SCALE)
4LSB' S
CURRENT
CELLS
6LSB' S
CURRENT
CELLS
CLOCK
GENERATOR
–
+
CURRENT CELLS
(FOR FULL SCALE)
BIAS VOLTAGE
GENERATOR
CXD2310R(SONY)
C-MOS 10-BIT 20MSPS VIDEO A/D CONVERTER
—TOP VIEW—
51
RO
50
RO
55
54
TSTR 37
59
BO
AT 38
58
BO
S/H
VIN 39
35
AMP.
VB
40 NC
CAL 41
TS 42
43 AGND
44 AGND
45 DV
DD
(+3V)
46 NC
47 NC
48 DGND
FINE LATCH
43
45
47
44
46
48
29 12
VRT D9
30 11
VRT D8
39 10
VIN D7
34 9
VRB D6
35 8
VRB D5
41 5
CAL D4
17 4
SEL D3
15 3
RESET D2
24 2
CE D1
23 1
OE D0
22
CLK
14 13
TIN TO
37 38
TSTR AT
42
TS
50
RO
51
RO
44
VGR
INPUT
31
CAL ; CALIBRATION PULSE INPUT
RCK
CE ; CHIP ENABLE
43
CLK ; CLOCK
ROR
40
LINV ; OUTPUT (D0-D8) INVERSION
VRR
MINV ; OUTPUT (D9) INVERSION
OE ; DIGITAL DATA OUTPUT ENABLE
37
IRR
RESET ; CALIBRATION CIRCUIT RESET
SEL ; OUTPUT DATA (D5-D9) SELECT FOR CALIBRATION (4-CLOCK)
HIGH; THROUGH OUTPUT, LOW; DATA FIXED AS WITH D0-D4
TIN ; TEST SIGNAL INPUT
TMOD ; TEST MODE
TS ; TEST SIGNAL INPUT
TSTR ; TEST SIGNAL INPUT
54 VRB ; REFERENCE BOTTOM VOLTAGE
GO
VRT ; REFERENCE TOP VOLTAGE
55
GO
46
VGG
OUTPUT
AT ; TEST SIGNAL OUTPUT
32
GCK
D0-D9 ; DIGIRAL DATA OUTPUT
TO ; TEST PIN
45
ROG
41
VRG
38
IRG
58
BO
59
BO
48
VGB
33
BCK
47
ROB
42
VRB
39
IRB
35
VB
COURSE
CONPARATE
& ENCODE
TIMING
GEN.
+
–
+
DAC
AMP.
(x 8)
DGND
FINE
COMPARATE
& ENCODE
COURSE CORRECTION
& LATCH
24 CE
23 OE
22 CLK
21 MINV
20 LINV
19 TMOD
AV 18
DD
(+5V)
17 SEL
16
15 RESET
14 TIN
13 TO
BVP-550