Sony BVP-550 Maintenance Manual page 598

IC
MC14023BF(MOTOROLA)FLAT PACKAGE
C-MOS 3-INPUT NAND GATE
— TOP VIEW —
14 13 12 11 10 9 8
V
DD
+3 V to
+18 V
GND
1 2 3 4 5 6 7
MC74HC00AF(MOTOROLA)FLAT PACKAGE
TC74HC00AF(TOSHIBA)FLAT PACKAGE
TC74VHC00FS(EL)(TOSHIBA)FLAT PACKAGE(SMALL)
C-MOS QUAD 2-INPUT NAND GATES
—TOP VIEW—
14 13 12 11 10 9 8
V
DD
GND
1 2 3 4 5 6 7
NOTE:
V
TYPE DD
TC74AC00 TYPE
+2 to +5.5V
TC74VHC00
+5V
MC74HCT00N
74ACT00 TYPE +4.5 to +5.5V
OTHER TYPES
+2 to +6V
MC74HC4053F(MOTOROLA)FLAT PACKAGE
TC74HC4053AFS(TOSHIBA)FLAT PACKAGE
C-MOS TRIPLE 2-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER
— TOP VIEW —
V
DD
Y1 1 16
IN/OUT
(+2 V to +6 V)
Y0 2 15 Y
IN/OUT IN/OUT
Z1 3 14 X
IN/OUT IN/OUT
Z 4 13 X1
IN/OUT IN/OUT
Z0 5 12 X0
IN/OUT IN/OUT
EN 6 11 A
IN IN
7 10 B
V * IN
EE
8 GND 9 C
IN
*
V ; V – V = +3 V to +12 V
EE DD EE
<
V GND
EE =
CONTROL INPUTS
SELECT ON CHANNEL
EN
C B A
0 0 0 0 Z0 Y0 X0
0 0 0 1 Z0 Y0 X1
0 0 1 0 Z0 Y1 X0
0 0 1 1 Z0 Y1 X1
0 1 0 0 Z1 Y0 X0
0 1 0 1 Z1 Y0 X1
0 1 1 0 Z1 Y1 X0
0 1 1 1 Z1 Y1 X1
1 X X X OPEN
6-16
A A
B Y = B Y
C C
Y = A • B • C = A + B + C
A B C Y
X X 0 1
X 0 X 1
0 ; LOW LEVEL
0 X X 1
1 ; HIGH LEVEL
1 1 1 0
; DON'T CARE
X
A A
Y =
Y
B
B
Y = A • B = A + B
A B Y
0 0 1
0 1 1
1 0 1
0 ; LOW LEVEL
1 1 0
1 ; HIGH LEVEL
12
X0
13 14
X1 X
OPEN
11 A
2 Y0
1 Y1 Y 15
OPEN
10 B
5
Z0
3 4
Z1 Z
OPEN
9 C
EN V
EE
6 7
0 ; LOW LEVEL
1 ; HIGH LEVEL
X ; DON'T CARE
MN6790S(MATSUSHITA)
C-MOS CLOCK GENERATOR
— TOP VIEW —
1 14 VCO1
D. GND IN
A. V
PC 2 DD 13
OUT
(+4.5 V to +5.5 V)
3 A. GND 12
D. V
DD
(+4.5 V to +5.5 V)
PC1 4 11 TEST2
IN OUT
PC2 5 10 TEST1
IN IN
DIV 6 9 MOD1
OUT IN
MOD2 7 8 CK
IN OUT
PC VCO1
OUT IN
2 14
4
PC1 IN
PHASE
VCO
5
COMPARATOR
PC2 IN
1
2
6
1
DIV OUT
684,858,864
8
CK OUT
FREQUENCY
MOD1 MOD2 VCO
RATIO
0 0 1/684
1 0 1/858 OSCILLATION
0 1 1/864
1 1 STANDSTILL
0 ; LOW LEVEL
1 ; HIGH LEVEL
4 2
PC1 PC
5
PC2
14 11
VCO1 TEST2
6
DIV
8
11
TEST2 OUT
MOTE
CK = DIV = L
BVP-550