System I/O Memory Map; Table 1-8. Pci 1 Domain I/O Map; Table 1-9. Device Bank 1 I/O Memory Map - Motorola MVME5500 Programmer's Reference Manual

Board Description and Memory Maps
1
PCI 1 I/O Address
Start
0000 0000

System I/O Memory Map

1-10

Table 1-8. PCI 1 Domain I/O Map

End Size
007F FFFF 8MB
System resources for the MVME5500 board including system control and
status registers, NVRAM/RTC, and the 16550 UARTs are mapped into a
1MB address range assigned to device bank 1. The region defined by
device bank 1 resides within the GT-64260B device bus register's space
listed in Table 1-3 on page
following table:

Table 1-9. Device Bank 1 I/O Memory Map

Device Bank1
Address Offset
0 0000
0 0001
0 0002
0 0003
0 0004
0 0005
0 0006
0 0007
0 0008 - 0 FFFF
1 0000 - 1 7FFF
2 0000 - 2 0FFF
2 1000 - 2 1FFF
2 4000 - F FFFF
Definition
Local PCI Domain I/O Space
1-6. The memory map is defined in the
Definition
System Status Register 1
System Status Register 2
System Status Register 3
Reserved
Presence Detect Register
Software Readable Header/Switch
Timebase Enable Register
Geographical Address Register (VME board)
Reserved for future on-board registers
M48T37V NVRAM/RTC
COM1 16550 UART
COM2 16550 UART
Reserved (undefined)
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