Falcon Flash Memory; System Memory - Motorola MTX Series Programmer's Reference Manual

Board Description and Memory Maps
1

Falcon FLASH Memory

System Memory

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The Falcon chipset supports up to two banks of FLASH memory. For the
MTX each bank is 8-bits wide. Bank A FLASH size can be determined
from the Memory Configuration Register. The maximum ROM/FLASH
size is 64M per bank.
The FLASH type information for each bank is available via the Memory
Configurator Register (MEMCR). The FLASH type information is helpful
in determining the correct programming algorithm for the actual FLASH
devices.
The reset vectors may be sourced by either Bank A or Bank B depending
on the state of rom_b_rv control bit. When rom_b_rv bit is cleared,
address range FFF00000-FFFFFFFF maps Bank A. When rom_b_rv bit
is set, it maps to Bank B.
The system memory is ECC-protected and is controlled by the Falcon
chipset. Up to two blocks of system memory are supported. Each block of
system memory can be up to 1GB in size. The design supports DRAM
speed as slow as 70ns. Both fast-page mode and hyper-page (EDO) mode
are supported. The best memory performance is achieved with 50ns EDO
devices.
Software needs to obtain the DRAM configuration information for each
block of memory by reading the DRAM serial presence detect (SPD)
information via the two wire serial bus. The SPD provides the size, speed
and type information for each DRAM DIMM device. The speed and
refresh mode information are required to initialize the ram_spd0,
ram_spd1, and ram_fref control bits in the Falcon's Revision ID/General
Control Register.
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