Falcon Chipset; Table 1-12. Typical Dimm Spd Information - Motorola MTX Series Programmer's Reference Manual

The maximum size of each DRAM block is 1GB.

Table 1-12. Typical DIMM SPD Information

Byte# Value
(hex)
0 0hxx
1 0h08
2 0h01
0h02
3 oh0C
4 0h0B
5 0h01
6 0h40
0h48
7 0h00
8 0h01
9 0h3C
0h46
10 0h0F
0h14
11 0h00
0h02
12 0h00
13
14

Falcon Chipset

The Falcon chipset consists of two identical Falcon ASIC devices; The
upper Falcon and the lower Falcon. The upper Falcon connects to the
upper half of the system data bus, DH00 through DH31, while the lower
Falcon connects to lower half of the system data bus, DL00 through DL31.
http://www.motorola.com/computer/literature
Entry
Value
x
256
Fast Page
EDO
12
11
1
x64
x72
0
LVTTL
60ns
70ns
15ns
20ns
None
ECC
15.6 us Normal Refresh rate/type
0h08 x8
0h00 Undefined
Description
Number of SPD bytes
Total # bytes in SPD EEPROM
Memory type
# of row addresses
# of column addresses
# of banks/DIMM
Module data width
Module data width (cont.)
Module interface levels
RAS access time
CAS access time
Error detect/correction
configuration
Primary DRAM organization
Secondary DRAM organization
Programming Model
1-15
1