Booting The Board; Reading Post Results; Table 9 Post Bit Layout Results - Motorola PPC/CPCI-690 Reference Manual

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PowerBoot

Booting the Board

Reading POST Results

PPC/CPCI-690
When the board is turned on or rebooted, the presence and functionality of
the board's components is tested by the power-on self test (POST). After
POST has finished, the board can either boot automatically or after entering
the autoboot command. The necessary boot parameters for the possibilities
have to be set via the setboot command. The parameters are stored in the
on-board NVRAM which keeps its contents during power-off and checks
them after the next power-on or after reset.
If POST is executed before the boot-up procedure or not, can be set in the
POST option in setboot. If POST is enabled and executed, its results are
stored in the NVRAM at offset 7CF8
Table 9:
POST Bit Layout Results
Bit
Description
0
DRAM testbit
1
PCI testbit
2
Not used
3
Boot flash test bit
4
Ethernet testbit
5
NVRAM testbit
6
Not used
7
Not used
A fully functional CPCI-690 will show the value 0x3B for all tests which are
okay. A failure will not stop the power-up process since debug functional-
ity is provided via console serial interface 1.
.
16
Result
1: Okay
0: Failure
1: Okay
0: Failure
0
1: Okay
0: Failure
1: Okay
0: Failure
1: Okay
0: Failure
0
0
Booting the Board
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