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16.1.3.1 SPI System Block Diagram
The following figure shows the SPI modules of two MCUs connected in a master-slave
arrangement. The master device initiates all SPI data transfers. During a transfer, the
master shifts data out (on the MOSI pin) to the slave while simultaneously shifting data
in (on the MISO pin) from the slave. The transfer effectively exchanges the data that was
in the SPI shift registers of the two SPI systems. The SPSCK signal is a clock output
from the master and an input to the slave. The slave device must be selected by a low
level on the slave select input (SS pin). In this system, the master device has configured
its SS pin as an optional slave select output.
MASTER
SPI SHIFTER
8 BITS
CLOCK
GENERATOR
16.1.3.2 SPI Module Block Diagram
The following is a block diagram of the SPI module. The central element of the SPI is the
SPI shift register. Data is written to the double-buffered transmitter (write to SPIx_D) and
gets transferred to the SPI shift register at the start of a data transfer. After shifting in 8
bits of data, the data is transferred into the double-buffered receiver where it can be read
from SPIx_D. Pin multiplexing logic controls connections between MCU pins and the
SPI module.
When the SPI is configured as a master, the clock output is routed to the SPSCK pin, the
shifter output is routed to MOSI, and the shifter input is routed from the MISO pin.
When the SPI is configured as a slave, the SPSCK pin is routed to the clock input of the
SPI, the shifter output is routed to MISO, and the shifter input is routed from the MOSI
pin.
Freescale Semiconductor, Inc.
MOSI
MISO
SPSCK
SS
Figure 16-1. SPI System Connections
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
Chapter 16 8-Bit Serial Peripheral Interface (8-bit SPI)
SLAVE
MOSI
SPI SHIFTER
MISO
8 BITS
SPSCK
SS
443
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