Bus Interface; Bus Controller - Panasonic MN101L Series User Manual

Chapter 2
CPU

2.2 Bus Interface

2.2.1

Bus Controller

The CPU provides separate buses to the internal memory and internal peripheral circuits to reduce bus line loads
and thus realize faster operation.
There are three buses: ROM bus, RAM bus, and peripheral extension bus (C-BUS). They connect to the internal
ROM, internal RAM, internal peripheral circuits respectively. The bus control block controls the parallel opera-
tion of instruction read and data access. Figure:2.2.1 shows functional block diagram of the bus controller.
Instruction
queue
Instruction
input bus
Data input bus
Data output bus
II - 14 Bus Interface
Program address
Address decoder
MUX MUX
ROM bus RAM bus
A D A
Internal ROM Internal RAM
Figure:2.2.1 Functional Block Diagram of the Bus Controller
Memory mode setting
Memory control register
D
Interrupt
Operand address
control
Bus controller
Interrupt bus
MUX
Peripheral extension
bus(C-BUS)
A D
Internal peripheral
functions